PM7312 pmc-sierra, PM7312 Datasheet - Page 87

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
10.9.14
The partial packet buffer processor is divided into three sections: reader, writer and roamer. The
roamer is a time-sliced state machine that tracks each HDLC channel’s FIFO buffer free space and
signals the writer to service a particular channel. The writer requests data from the EQM-12 block
and transfers packet data from the EQM-12 to the associated HDLC channel FIFO. The reader is a
time-sliced state machine that transfers the HDLC information from an HDLC channel FIFO to the
HDLC processor in response to a request from the HDLC processor. If a buffer under-run occurs
for an HDLC channel, the reader informs the HDLC processor and purges the rest of the packet. If
a buffer overflow occurs for an HDLC channel (this can only happen if EQM-12 disregards the
requests), the THDL-12 overwrites the FIFO contents resulting in data corruption on that particular
HDLC channel. When an underflow or an overflow occurs, an interrupt is generated and the cause
of the interrupt may be read via the interrupt status register using the microprocessor interface.
The writer and reader determine empty and full FIFO conditions using flags. Each block in the
partial packet buffer has an associated flag. The writer sets the flag after the block is written and
the reader clears the flag after the block is read. The flags are initialized (cleared) when the block
pointers are written using indirect block writes. The reader declares an HDLC channel FIFO under-
run whenever it tries to read data from a block without a set flag.
The FIFO algorithm of the partial packet buffer processor is based on per- HDLC channel software
programmable transfer size and free space trigger level. Instead of tracking the number of full
blocks in an HDLC channel FIFO, the processor tracks the number of empty blocks, called free
space, as well as the number of end of packets stored in the FIFO. Recording the number of empty
blocks instead of the number of full blocks reduces the amount of information the roamer must
store in its state RAM.
The partial packet roamer records the FIFO free space and end-of-packet count for all HDLC
channel FIFOs. When the reader signals that a block has been read, the roamer increments the
FIFO free space and sets a per- HDLC channel request flag if the free space is greater than the
hungry or starving threshold. The roamer pushes this status information to the EQM to indicate that
it can accept at least one transfer of data. The roamer also decrements the end-of-packet count
when the reader signals that it has passed an end of a packet to the HDLC processor. The roamer
listens to control information from the EQM-12 to decide which HDLC channel FIFO requests data
from the EQM block. The roamer informs the partial packet writer of the HDLC channel FIFO to
process and the FIFO free space. The writer sends a request for data to the EQM-12 block, writes
the response data to the HDLC channel FIFO, and sets the block full flags. The writer reports back
to the roamer the number of blocks and end-of-packets transferred. The maximum amount of data
transferred during one request is set by XFER.
The roamer round-robins between all HDLC channels FIFOs and pushes the status to the EQM-12
block. The status consists of two pieces of information: (1) is there space in the HDLC channel
FIFO for at least 32 bytes of data, and (2) is this channel FIFO at risk of underflowing.
The configuration of the HDLC processor is accessed using indirect channel read and write
operations as well as indirect block read and write operations. When an indirect operation is
performed, the information is accessed from RAM during a null clock cycle identified by the
TCAS-12 block. Writing new provisioning data to an HDLC channel resets the entire state vector.
Transmit Channel Assignor (TCAS-12)
The Transmit Channel Assignor block (TCAS-12) processes up to 1024 HDLC channels. Data for
all HDLC channels is sourced from a single byte-serial stream from the Transmit HDLC Controller
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
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