PM7312 pmc-sierra, PM7312 Datasheet - Page 59

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
10.2 Memory Port
10.2.1
10.2.2
10.3 Packet Walkthrough
10.3.1
Writing
Write operations to external memory can be performed in up to 4-long word bursts to the memory
port. The procedure is as follows:
1. The microprocessor polls the MPBusy bit of the Memory Port Control register (or monitors the
2. The microprocessor writes up to 4 long words of data into the write burst register array and the
3. The microprocessor writes a command to the memory burst control register. The command
4. FREEDM 32A1024L arbitrates for the appropriate memory, performs the write to memory, and
Reading
Reads from external memory can be performed in 4-long word bursts from the memory port. The
procedure is as follows:
1. The microprocessor issues a read command to the Memory Port Control register. The
2. FREEDM 32A1024L arbitrates for the appropriate memory, performs the read from memory
3. The microprocessor polls the MPBusy bit of the Memory Port Control register status (or
4. The microprocessor reads up to 4 long words of data from the read burst register array and the
Ingress Path
Figure 14 shows the elements and data transformations that occur as data traverses the FREEDM
32A1024L from the SBI to the Any-PHY interface.
MPISTATI interrupt) to verify that the previous write is complete. Alternatively, this step may
be skipped if the system application allows FREEDM 32A1024L to withhold the READYB for
write accesses. In this case, FREEDM 32A1024L will delay write operations to the write burst
registers and overflow register until the previous write command is complete.
overflow register (for 48-bit accesses).
indicates the aperture, the quad-long word address in memory, the type of write (masked or
unmasked), and the 4 long word enables. MPBusy will be set until the write is complete.
clears the MPBusy bit in the control register.
command indicates aperture, the quad-long word address in memory, and 4 long word enables.
The MPBusy bit will be set by the FREEDM 32A1024L.
and loads the read burst registers with the results, and clears the MPBusy bit in the control
register.
monitors the MPISTATI interrupt) to verify that the read is complete. Alternatively, this step
may be skipped if the system application can tolerate long response times for read accesses. In
this case, FREEDM 32A1024L will delay read operations from the read burst registers and
overflow register until the read command is complete.
overflow register (for 48-bit accesses).
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
59