PM7312 pmc-sierra, PM7312 Datasheet - Page 46

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Pin Name
READYB
BTERMB
WRDONEB
INTHIB
INTLOB
BUSPOL
Table 8 Miscellaneous Interface Signals (10 Pins)
Pin Name
SYSCLK
Type
Type
Tri-state
Output
Tri-state
Output
Output
OD
OD
Input
Input
Pin No.
E12
D12
C12
B12
A12
E13
Pin No.
H1
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
Function
Ready Bar. This active low signal indicates that data on the
AD[31:0] bus has been accepted (for writes), or data on the
AD[31:0] is valid (for reads). This signal may be used by FREEDM
32A1024L to delay a data transaction. This output is tristated one
clock cycle after an FREEDM 32A1024Laccess, allowing multiple
slave devices to be tied together in the system. This output should
be pulled up externally.
READYB is updated on the rising edge of BCLK.
Burst Terminate Bar. This signal is asserted low by FREEDM
32A1024L when a data transfer has reached the address boundary
of a burstable range. The maximum burst range supported is 4.
Attempts to extend the burst transfer after this signal is asserted
will be ignored. This output is tristated one clock cycle after an
FREEDM 32A1024Laccess, allowing multiple slave devices to be
tied together in the system. This output should be pulled up
externally.
BTERMB is updated on the rising edge of BCLK.
Write Done Bar. This signal is asserted low by FREEDM
32A1024Lwhen the most recent write access to internal registers is
complete. This signal may be used by external circuitry to delay
the issuance of a write operation address cycle until FREEDM
32A1024Lcan accept write data. This signal is only needed in
systems where the READYB output cannot be used to delay a
write data transaction (due to microprocessor restrictions).
WRDONEB is updated on the rising edge of BCLK.
Active Low Open-Drain High Priority Interrupt. This signal goes low
when a FREEDM 32A1024L high priority interrupt source is active
and that source is unmasked. The FREEDM 32A1024Lmay be
enabled to report many alarms or events via interrupts. INTHIB
becomes high impedance when the interrupt is acknowledged via
an appropriate register access.
INTHIB is an asynchronous signal.
Active Low Open-Drain Low Priority Interrupt. This signal goes low
when a FREEDM 32A1024L low priority interrupt source is active
and that source is unmasked. The FREEDM 32A1024Lmay be
enabled to report many alarms or events via interrupts. INTLOB
becomes high impedance when the interrupt is acknowledged via
an appropriate register access.
INTLOB is an asynchronous signal.
Bus Control Polarity. This signal indicates the polarity of the WR
and BLAST inputs to FREEDM 32A1024L.
When high, the BLAST pin is active high (high indicates the last
word of the burst) and the WR pin is active low (low indicates
write).
When low, the BLAST pin is active low (low indicates the last word
of the burst) and the WR pin is active high (high indicates write).
BUSPOL is sampled on the rising edge of BCLK.
The system clock (SYSCLK) provides timing for the core logic.
SYSCLK is nominally a 50% duty cycle clock of frequency 100
MHz ±50ppm.
Released
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