PM7312 pmc-sierra, PM7312 Datasheet - Page 138

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Register 0x388: THDL Indirect Channel Data #2
This register contains data to be inserted into the channel provision RAM in an indirect write
operation.
FLEN[10:0]
Reserved
DFCS
The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that is provisioned to
the circular channel FIFO specified by the FPTR[10:0] block pointer. The FIFO length to be
written to the channel provision RAM, in an indirect channel write operation, must be set up in
this register before triggering the write.
The reserved bits must be set low for correct operation of the FREEDM 32A1024L device.
The diagnose frame check sequence bit (DFCS) controls the inversion of the FCS field inserted
into the transmit packet. The value of DFCS to be written to the channel provision RAM, in an
indirect channel write operation, must be set up in this register before triggering the write.
When DFCS is set to one, the FCS field in the outgoing HDLC stream is logically inverted
allowing diagnosis of downstream FCS verification logic. The outgoing FCS field is not
inverted when DFCS is set to zero. DFCS reflects the value written until the completion of a
subsequent indirect channel read operation.
Bit
Bit 31
To
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
7BIT
INHIBIT
INVERT
DFCS
Reserved
FLEN[10]
FLEN[9]
FLEN[8]
FLEN[7]
FLEN[6]
FLEN[5]
FLEN[4]
FLEN[3]
FLEN[2]
FLEN[1]
FLEN[0]
Default
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
Released
138