PM7312 pmc-sierra, PM7312 Datasheet - Page 258

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
driven high. This is the case for the first burst data transfer in Figure 43. In the second burst data
transfer, the FREEDM 32A1024L drives the TRDY signal low to indicate that the FIFO in the Tx
APPI is full and no further data may be transferred. Upon sampling the TRDY signal low, the
external controller must hold the last valid word of data on TXDATA[15:0]. The FREEDM
32A1024L may drive TRDY low for an indeterminate number of TXCLK cycles. During this time,
the external controller must wait and is not permitted to begin another burst data transfer until
TRDY is sampled high. When there is space in the Tx APPI FIFO, the FREEDM 32A1024L drives
the TRDY signal high. Upon sampling the TRDY signal high, the external controller completes the
current burst data transfer. The FREEDM 32A1024L tristates the TRDY signal one TXCLK cycle
after it has been driven high.
The external controller must sample the TRDY signal high and must then wait one clock cycle
before it can begin the next burst data transfer. This prevents the external controller from
bombarding the FREEDM 32A1024L device with small packets and allows the FREEDM
32A1024L to perform the necessary housekeeping and clean up associated with the ending of burst
data transfers. In addition, the rule that TSX must be a minimum of 4 clock cycles apart must be
adhered to. This protocol also ensures that transitions between burst data transfers do not require
any extra per Any-PHY channel storage, thereby simplifying implementation of both the external
controller and the FREEDM 32A1024L device. Figure 44 illustrates this condition.
Figure 44 Transmit APPI Timing (Special Conditions)
Figure 44 shows two special conditions – (1) the transfer of a one word packet, illustrating how the
external controller must wait until TRDY has been sampled high before the next data transfer can
begin, and (2) the transfer of a packet that completes when TRDY is set low, illustrating that
although the packet has been completely transferred, the external controller must still wait until
TRDY has been sampled high before the next data transfer can begin.
The first data transfer is a single word packet for Any-PHY channel 0. The FREEDM 32A1024L
asserts TRDY high one TXCLK cycle after TSX is sampled high. The Tx APPI protocol dictates
that the external controller must wait until one clock after TRDY is sampled high before beginning
the next data transfer for Any-PHY channel 3. The external controller must hold the last valid word
on TXDATA[15:0] until TRDY is sampled high. In this case, that data is a don’t care. The
FREEDM 32A1024L tristates the TRDY signal one TXCLK cycle after it has been driven high.
The second transfer is a three word packet, which completes transfer in the same TXCLK cycle that
TRDY is sampled low by the external controller. Again, the external controller must hold the last
valid word on TXDATA[15:0] until TRDY is sampled high. In this case, that data is D2, the last
word of the packet. The FREEDM 32A1024L may drive TRDY low for an indeterminate number
of TXCLK cycles. During this time, the external controller must wait and is not permitted to begin
TXDATA[15:0]
TXCLK
TMOD
TRDY
TEOP
TERR
TSX
CH 0
D0
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
CH 3
D0
D1
D2
CH 2
D0
Released
258