PM7312 pmc-sierra, PM7312 Datasheet - Page 45

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Pin Name
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
ADSB
CSB
WR
BURSTB
BLAST
Type
I/O
Input
Input
Input
Input
Input
Pin No.
F3
E1
F4
E2
F5
E3
D2
E4
D5
B4
C5
E6
B5
D6
A5
C6
E7
B6
D7
C7
B7
A7
D8
C8
B8
E9
A8
D9
E10
A9
D10
C10
B10
A10
D11
C11
B11
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
Multiplexed Address Data Bus. The multiplexed address data bi-
directional bus AD[31:0] is used to connect the FREEDM
32A1024L to the microprocessor.
During the address phase when ADSB = 0, AD[1:0] are ignored as
all transfers are 32 bits wide.
AD[31:0] is sampled/updated/tristated on the rising edge of BCLK.
Address Status. This signal is active-low and indicates a long-word
address is present on the address/data bus AD[31:2].
ADSB is sampled on the rising edge of BCLK.
Active Low Chip Select. The chip select (CSB) signal is low during
the address cycle (as defined by ADSB) FREEDM 32A1024L
register accesses.
CSB is sampled on the rising edge of BCLK.
Write/Read. The write/read (WR) signal is evaluated when the
ADSB and CSB are sampled active by FREEDM 32A1024L. The
BUSPOL input pin controls the polarity of this input.
WR is sampled on the rising edge of BCLK.
Burst Bar. This signal is evaluated when the ADSB and CSB are
sample active by FREEDM 32A1024L. When low, this signal
indicates that the current access is a burst access (and the BLAST
input can be used to detect the end of the transaction).
BURSTB is sampled on the rising edge of BCLK.
Burst Last. This signal indicates the last data access of the
transfer. When the BURSTB input is low, the BLAST input is
driven active during the last transfer of a transaction (even if the
transaction is one word in length). When the BURSTB input is
high, the BLAST input is ignored by FREEDM 32A1024L. The
BUSPOL input pin controls the polarity of this input.
BLAST is sampled on the rising edge of BCLK.
Released
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