PM7312 pmc-sierra, PM7312 Datasheet - Page 145

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
AVAIL
DMAREQ
DMAEXP
The indirect channel data available flag (AVAIL) indicates when sufficient packet data is store
in the channel FIFO for the HDLC processor to start transmission. When AVAIL is high, the
channel FIFO free space is less than or equal to the level specified by the TRANS and
LEVEL[3:0] register bits or at least one end of packet is store in the channel FIFO. In this case,
the HDLC processor starts transmission when AVAIL is high and sufficient flags/idle specified
by FLAG[2:0] have been transmitted. When AVAIL is low, the channel FIFO free space is
greater than the level specified by the TRANS and LEVEL[3:0] register bits and no end of
packets are store in the channel FIFO. In this case, the HDLC processor will not start
transmitting a new packet or will finish transmitting the current packet. AVAIL reflects the
value of the last indirect channel read operation.
The AVAIL register bit is used for test purposes only.
The indirect channel service request flag (DMAREQ) indicates when sufficient free space
exists in the channel FIFO to perform a DMA operation. When DMAREQ is high, the channel
free space is greater than or equal to 32 bytes. When DMAREQ is low, the channel free space
is less than 32 bytes. DMAREQ reflects the value of the last indirect channel read operation.
The DMAREQ register bit is used for test purposes only.
The indirect channel expedite service request flag (DMAEXP) indicates when the channel
FIFO requires an expedited DMA operation. When DMAEXP is high, the channel free space is
greater than or equal to the level specified by LEVEL[3:0] and the HDLC processor is
transmitting a packet and the end of a packet is not store in the channel FIFO. When DMAEXP
is low, the channel free space is less than the level specified by LEVEL[3:0], or the HDLC
processor is not transmitting or an end of a packet is store in the channel FIFO. DMAEXP
reflects the value of the last indirect channel read operation.
The DMAEXP register bit is used for test purposes only.
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
145