PM7312 pmc-sierra, PM7312 Datasheet - Page 254

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
14.3 Receive APPI Timing (Any-PHY Level 2)
RXADDR[3:0]
The receive Any-PHY packet interface (APPI) timing is shown in Figure 39 through Figure 42
when the Any-PHY interface operates at 52 MHz, 16 bits of RXDATA are valid. The FREEDM
32A1024L device provides data to an external controller using the receive APPI. The following
discussion surrounding the receive APPI functional timing assumes that multiple FREEDM
32A1024L devices share a single external controller. All Rx APPI signals are shared between the
FREEDM 32A1024L devices
Figure 39 Receive APPI Timing (Normal Transfer 16 bit 52 MHz)
XDATA[15:0]
Figure 39 shows the transfer of an 8 word packet across the Rx APPI from FREEDM 32A1024L
device 0, Any-PHY channel 2. In this example, seven FREEDM 32A1024L devices are sharing the
Rx APPI, with device 5 being the null address.
The data transfer begins when the external controller selects FREEDM 32A1024L device 0 by
placing that address on the RXADDR[3:0] inputs and setting RENB high. The external controller
sets RENB low in the next RXCLK cycle to commence data transfer across the Rx APPI. The
FREEDM 32A1024L samples RENB low and responds by asserting RSX one RXCLK cycle later.
The start of all burst data transfers is qualified with RSX and an in-band Any-PHY channel address
on RXDATA[15:0] to associate the data to follow with an Any-PHY channel.
During the cycle when D2 is placed on RXDATA[15:0], the external controller is unable to accept
any further data and sets RENB high. Two RXCLK cycles later, the FREEDM 32A1024L tristates
the Rx APPI. The external controller may hold RENB high for an indeterminate number of
RXCLK cycles. The FREEDM 32A1024L will wait until the external controller returns RENB
low. Because the FREEDM 32A1024L does not support interrupted data transfers on the Rx APPI,
the external controller must reselect FREEDM 32A1024L device 0 or output a null address during
the clock cycle before it returns RENB low. However, while RENB remains high, the address on
the RXADDR[3:0] signals may change. When the FREEDM 32A1024L device 0 samples RENB
low, it continues data transfer by providing D4 on RXDATA[15:0]. Note that if D3 were the final
word of the packet (Status), in response to sampling REOP high, the external controller does not
have to reselect FREEDM 32A1024L device 0. This is shown in Figure 42.
The FREEDM 32A1024L will not pause burst data transfers across the Rx APPI.
RXCLK
RMOD
REOP
RERR
RENB
RSOP
RVAL
RPA
RSX
Dev 0
NULL
Dev 7
Dev 0
NULL
CH 2
Dev 6
Dev 7
D0
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Dev 0
Dev 0
NULL
D1
Dev 6
Dev 4
D2
NULL
D3
Dev 0
Dev 4
NULL
Dev 1
Dev 0
NULL
D4
Dev 3
Dev 1
D5
Dev 0
Dev 0
NULL
D6
Dev 2
Dev 3
D7
Released
254
NULL
Dev 2