PM7312 pmc-sierra, PM7312 Datasheet - Page 29

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
9
Pin Description
Table 2 SBI Interface Signals (30 Pins)
Pin Name
REFCLK
DC1FP
AC1FP
C1FPOUT
DDATA[0]
DDATA[1]
DDATA[2]
DDATA[3]
DDATA[4]
DDATA[5]
DDATA[6]
DDATA[7]
Type
Input
Input
Input
Output
Input
Pin No.
P30
P31
K30
K31
R27
R28
R29
R30
R31
U31
U30
U27
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
The SBI reference clock signal (REFCLK) provides reference
timing for the SBI ADD and DROP buses.
REFCLK is nominally a 50% duty cycle clock of frequency 19.44
MHz ±50ppm for SBI bus operation or 77.76 MHz ±20ppm for
SBI336 bus operation
The C1 octet frame pulse signal (DC1FP) for the drop bus provides
frame synchronization for devices connected via an SBI interface.
DC1FP must be asserted for 1 REFCLK cycle every 500 µs or
multiples thereof (i.e. every 38880 x n REFCLK cycles, where n is
a positive integer). All devices interconnected via the SBI drop
interface must be synchronized to a DC1FP signal from a single
source.
DC1FP is sampled on the rising edge of REFCLK.
Note – If the SBI bus is being operated in synchronous mode,
DC1FP must be asserted for 1 REFCLK cycle every 6 ms or
multiples thereof.
The C1 octet frame pulse signal (AC1FP) for the add bus provides
frame synchronization for devices connected via an SBI interface.
AC1FP must be asserted for 1 REFCLK cycle every 500 µs or
multiples thereof (i.e. every 38880 n REFCLK cycles, where n is a
positive integer). All devices interconnected via the add SBI
interface must be synchronized to an AC1FP signal from a single
source.
AC1FP is sampled on the rising edge of REFCLK.
Note – If the SBI bus is being operated in synchronous mode,
AC1FP must be asserted for 1 REFCLK cycle every 6 ms or
multiples thereof.
The C1 octet frame pulse output signal (C1FPOUT) may be used
to provide frame synchronization for devices interconnected via an
SBI interface. C1FPOUT is asserted for 1 REFCLK cycle every
500 µs (i.e. every 38880 REFCLK cycles).
C1FPOUT is updated on the rising edge of REFCLK.
Note – The C1FPOUT pulse is not suitable for use in systems in
which the SBI bus is operated in synchronous mode.
The SBI DROP bus data signals (DDATA[7:0]) contain the time
division multiplexed receive data from the up to 32 independently
timed links. Data from each link is transported as a tributary within
the SBI TDM bus structure. Multiple PHY devices can drive the
SBI DROP bus at uniquely assigned tributary column positions.
DDATA[7:0] are sampled on the rising edge of REFCLK.
Released
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