PM7312 pmc-sierra, PM7312 Datasheet - Page 67

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-
32 function. Figure 17 shows a CRC encoder block diagram using the generating polynomial g (X)
= 1 + g
generating polynomial g (X) = 1 + X
a generating polynomial g (X) = 1 + X + X
X
Figure 17 CRC Generator
The partial packet buffer processor controls the 64 Kbyte partial packet RAM, which is divided into
4K 16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular
HDLC channel FIFO buffers. Thus, non-contiguous sections of the RAM can be allocated in the
partial packet buffer RAM to create an HDLC channel FIFO. System software is responsible for
the assignment of blocks to individual HDLC channel FIFOs. Figure 18 shows an example of three
blocks (blocks 1, 3, and 200) linked together to form a 48 byte HDLC channel FIFO.
Partial Packet Buffer Processor
22
+ X
1
X + g
23
+ X
2
X
26
2
+ X
+…+ g
D
0
32
LSB
. The first FCS bit received is the residue of the highest term.
n-1
g
X
1
n-1
D
+ X
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
1
5
n
+ X
. The CRC-CCITT FCS is two bytes in size and has a
g
12
Parity Check Digits
2
2
+ X
+ X
D
4
16
2
+ X
. The CRC-32 FCS is four bytes in size and has
5
+ X
7
g
n-1
+ X
8
D
n-1
+ X
MSB
10
+ X
Message
11
+ X
12
+ X
Released
16
67
+