PM7312 pmc-sierra, PM7312 Datasheet - Page 256
![no-image](/images/no-image-200.jpg)
PM7312
Manufacturer Part Number
PM7312
Description
Freedm 32a1024l Assp Telecom Standard Datasheet
Manufacturer
pmc-sierra
Datasheet
1.PM7312.pdf
(283 pages)
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
0 by setting RENB high and placing address 0 on the RXADDR[3:0] signals. When the FREEDM
32A1024L samples RENB low, it begins the next data transfer as before.
Figure 41 Receive APPI Timing (Optimal Reselection)
RXDATA[15:0]
Figure 41 shows optimal bandwidth utilization across the Rx APPI.
With knowledge that the maximum burst data transfer (excluding Any-PHY channel address
prepend) is 256 bytes, i.e. 128 words, the external controller sets RENB high when the 127
(D126) is placed on RXDATA[15:0] in anticipation of the end of a burst transfer. The FREEDM
32A1024L completes the burst data transfer and tristates the Rx APPI one RXCLK cycle after
RENB is sampled high. Because the burst data transfer is complete and RENB is immediately
returned low following selection, the FREEDM 32A1024L immediately begins the next data
transfer following the single turn-around cycle.
The protocol dictates that at least one tristate turn-around cycle be inserted between data transfers,
even if the external controller is reselecting the same FREEDM 32A1024L device. In other words,
Figure 41 shows the earliest possible time that the external controller could have set RENB high to
reselect FREEDM 32A1024L device 0.
Figure 42 Receive APPI Timing (Boundary Condition)
RXDATA[15:0]
RXADDR[3:0]
RXADDR[3:0]
RXCLK
RXCLK
RMOD
RMOD
REOP
RSOP
REOP
RENB
RERR
RENB
RERR
RVAL
RVAL
RSOP
RPA
RSX
RPA
RSX
Dev 0
Dev 0
NULL
NULL
Dev 7
Dev 0
Dev 7
Dev 0
NULL
CH 2
NULL
CH 2
Dev 6
Dev 7
D0
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Dev 6
Dev 7
NULL
D0
D1
Dev 6
Dev 4
D2
NULL
D1
Dev 0
Dev 0
D3
NULL
D125
NULL
Dev 4
Dev 0
D126
Dev 7
NULL
D127
Dev 1
Dev 7
NULL
Dev 4
Dev 0
Dev 3
Dev 1
CH 1
CH 2
Dev 0
Dev 0
NULL
Dev 7
Dev 7
NULL
D8
Dev 4
D128
Released
Dev 2
Dev 3
th
D9
256
word
Dev 3
NULL
NULL
Dev 2
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