PM7312 pmc-sierra, PM7312 Datasheet - Page 63

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
10.5.1
10.5.2
10.6 Any-PHY Tear Down Procedure
CB and RS Memory FPP Initialization
1. After a hardware or software reset is issued, the chip goes into an initialization sequence. The
2. Wait for SDRAM_INIT to be cleared in XX_DRAMC Status and Control Registers
3. Test memories if desired by s/w.
4. FPP FIFO Initialization
5. Initialization Complete
Connection Initialization for Sequenced Links
6. When adding a connection to a multi-link bundle (including first connection setup), the
Before tearing down an Any-PHY channel, all CI’s associated with that Any-PHY channel must be
torn down according to the procedure described in section 10.7. In addition, the data must be
drained for the channel. This is done by:
1. Unprovision RCAS channel
RST_DONEI bit in the F32 Master High Priority Interrupt Status register will indicate when
this sequence is complete. At this stage, all the registers and memories internal to the chip and
the external SRAM can be accessed.
(PROV_MODE will also be set at this point).
o Option 1 (s/w init)
o Option 2 (h/w init)
FREEDM 32A1024L takes the first sequence number it receives to start re-sequencing. Due to
differential delay between links, if this isn’t the fastest link, this might not be the start of packet.
All subsequent fragments with lower sequence numbers will not be included in the re-
sequencing and will be sent out the Any-PHY tagged as unexpected sequence number. The
number of packets tagged as USN will depend on packet size and egress scheduling algorithm.
Once the first re-sequenced packet is complete (if in packet out mode), this packet will be sent
out missing the first few fragments but will not be tagged as erred. This may happen with every
new connection.
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Write ECC_OFF bit as desired
Write to the memory setting up the FPP FIFO as described in the XX_DRAMC
memory map descriptions
Write FUNC_MODE=1 and PROV_MODE=0 in the XX_DRAMC Status and
Control Registers
Write ECC_OFF bit to 1
Write FPP_INIT bit =1 and PROV_MODE=0 in the XX_DRAMC Status and
Control Registers
Wait for FUNC_MODE to be set indicating completion (PROV_MODE will also
be cleared)
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
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