PM7312 pmc-sierra, PM7312 Datasheet - Page 115

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Register 0x070: DLL Delay Tap Status
The DLL Delay Tap Status Register indicates the delay tap used by the DLL to generate the
outgoing clock.
Writing to this register performs a software reset of the DLL. A software reset requires a maximum
of 24*256 DLLSYSCLK cycles for the DLL to regain lock. During this time the DLLDCLKO
phase is adjusting from its current position to delay tap 0 and back to a lock position.
TAP[7:0]
The tap status register bits (TAP[7:0]) specifies the delay line tap the DLL is using to generate
the outgoing clock DLLDCLKO.
When TAP[7:0] is logic zero, the DLL is using the delay line tap with minimum phase delay.
When TAP[7:0] is equal to 255, the DLL is using the delay line tap with maximum phase delay.
TAP[7:0] is invalid when vernier enable VERN_EN is set to one.
Bit
Bit 31
To
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
Unused
TAP[7]
TAP[6]
TAP[5]
TAP[4]
TAP[3]
TAP[2]
TAP[1]
TAP[0]
Default
X
X
X
X
X
X
X
X
X
Released
115