PM7312 pmc-sierra, PM7312 Datasheet - Page 18

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
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2.1
2.2
Features
The PM7312 FREEDM 32A1024L is a Frame Engine and Data Link Manager with these features:
Interfaces
Channelization / HDLC Features
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o The interface is capable of supporting full datagram transfer on a per Any-PHY channel
o Fragmented packets or frames on a per Any-PHY channel basis.
Single-chip multi-channel HDLC controller with either a 52 MHz 16 bit Any-PHY Level 2 or
a 104 MHz 8 bit Any-PHY Level 3 packet interface for transfer of packet, frame data using
an external controller.
Supports line rate throughput for 32 T1s or E1s. (40 byte packets encapsulated in PPP over
HDLC (50 byte transfers (RFC 1661) or 55 byte transfers (RFC 1990))).
Provides simultaneous support of PPP, Frame Relay, multi-link-PPP and multi-link-Frame
Relay protocols. Alternative protocols supported via HDLC termination and full packet store
of the data within the HDLC structure.
Supports 2 levels of priority queuing in the egress direction. When the device is configured
to fragment low priority traffic, high priority traffic, if present, will be inserted in between
low priority fragments on a link.
A 52MHz, 16-bit Any-PHY Level 2 or 104MHz, 8-bit Any-PHY Level 3 packet interface for
system side connection.
A single 19.44 MHz SBI or 77.76 MHz SBI336 bus supporting up to 32 links.
A 100 MHz, 48-bit SDRAM interface for ingress and egress per packet/fragment storage.
A 100 MHz, 32-bit SDRAM interface for ingress re-sequencing data structures.
A 100 MHz, 36-bit SSRAM interface for Ingress/Egress Context storage.
The device provides the standard 5 signal P1149.1 JTAG test port for boundary scan.
A 32-bit microprocessor interface for configuration and status monitoring.
Support for up to 1024 HDLC channels in both the ingress and egress direction, with
individual HDLC channel speeds ranging from 56Kbps to 2 Mbps.
The 1024 HDLC channels can be assigned to a mixture of physical links via the SBI
interface. The SBI transports the equivalent of 3 STS-1 synchronous payload envelopes
(SPE). Each STS-1 SPE can be individually configured to carry 28 T1/J1s or 21 E1s. The
FREEDM 32A1024 can flexibly carry up to 32 T1s or E1s on these SPEs.
In a channelized application, the number of time-slots assigned to an HDLC channel is
programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1).
For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-
stuffing and frame check sequence validation. The receiver supports the validation of both
CRC-CCITT and CRC-32 frame check sequences.
basis or
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Released
18