PM7312 pmc-sierra, PM7312 Datasheet - Page 261

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
first burst data transfer in Figure 47. In Figure 48, the FREEDM 32A1024L drives the TRDY
signal low to indicate that the FIFO in the Tx APPI are full and no further data may be transferred.
Upon sampling the TRDY signal low, the external controller must hold the last valid word of data
on TXDATA[7:0]. The FREEDM 32A1024L may drive TRDY low for an indeterminate number of
TXCLK cycles. During this time, the external controller must wait and is not permitted to begin
another burst data transfer until TRDY is sampled high. Upon sampling the TRDY signal high, the
external controller completes the current burst data transfer.
The external controller can sample the TRDY signal high before it can begin the next burst data
transfer. TRDY is provided to prevent the external controller from bombarding the FREEDM
32A1024L device with small packets and allows the FREEDM 32A1024L to perform the necessary
housekeeping and clean up associated with the ending of burst data transfers. In addition, the rule
that TSX must be a minimum of 4 clock cycles apart must be adhered. This protocol also ensures
that transitions between burst data transfers do not require any extra per Any-PHY channel storage,
thereby simplifying implementation of both the external controller and the FREEDM 32A1024L
device. Figure 48 illustrates this condition.
Figure 48 Transmit APPI Timing Any-PHY Level 3 (Special Condition)
Figure 48 shows a special condition where the transfer of a packet that completes when TRDY is
set low, illustrating that although the packet has been completely transferred, the external controller
must still wait until TRDY has been sampled high before the next data transfer can begin.
The illustrated transfer is a two byte packet, which completes transfer in the same TXCLK cycle
that TRDY is sampled low by the external controller. The external controller must hold the last
valid byte on TXDATA[7:0] until TRDY is valid and sampled high. In this case, that data is D1, the
last byte of the packet. The FREEDM 32A1024L may drive TRDY low for an indeterminate
number of TXCLK cycles. During this time, the external controller must wait and is not permitted
to begin another burst data transfer until TRDY is valid and sampled high. When the external
controller samples TRDY high, the current burst transfer is deemed to be complete and the external
controller may begin the next data transfer.
Figure 49 Transmit APPI Polling Timing (Any-PHY Level 3)
TPA_LO, TPA_HI
TXADDR[15:0]
TXCLK
TXDATA[7:0]
TXCLK
TERR
TRDY
TEOP
TSX
CH 1023
CH 0
CH 1023
CH 254
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
CH 8
CH 0
CH 3
CH3
CH 254
D0
NULL
CH 8
D1
CH 0
CH2
CH 399
CH2
CH 0
D0
NULL
D1
Released
261
NULL1
CH 399