PM7312 pmc-sierra, PM7312 Datasheet - Page 12

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Figure 31 4-Bank Configuration for 8 MB of ZBT or Standard SSRAM ..................................... 83
Figure 32 2-Bank Configuration for Eight Mbit/s of ZBT-Compatible or Standard
Figure 33 1-Bank Configuration for Eight Mbit/s of ZBT or Standard SSRAM .......................... 85
Figure 34 Partial Packet Buffer Structure................................................................................... 86
Figure 35 Boundary Scan Architecture .................................................................................... 249
Figure 36 TAP Controller Finite State Machine........................................................................ 250
Figure 37 T1/E1 Drop Bus Functional Timing .......................................................................... 253
Figure 38 T1/E1 Add Bus Adjustment Request Functional Timing.......................................... 253
Figure 39 Receive APPI Timing (Normal Transfer 16 bit 52 MHz) .......................................... 254
Figure 40 Receive APPI Timing (Auto Deselection) ................................................................ 255
Figure 41 Receive APPI Timing (Optimal Reselection) ........................................................... 256
Figure 42 Receive APPI Timing (Boundary Condition) ............................................................ 256
Figure 43 Transmit APPI Timing (Normal Transfer) ................................................................ 257
Figure 44 Transmit APPI Timing (Special Conditions)............................................................. 258
Figure 45 Transmit APPI Poll Timing ....................................................................................... 259
Figure 46 Receive APPI Timing (Normal Transfer 8 bit 104 MHz) .......................................... 259
Figure 47 Transmit APPI Timing Any-PHY Level 3 (Normal Transfer) .................................... 260
Figure 48 Transmit APPI Timing Any-PHY Level 3 (Special Condition) .................................. 261
Figure 49 Transmit APPI Polling Timing (Any-PHY Level 3) ................................................... 261
Figure 50 Read Timing for Re-Sequencing Memory ............................................................... 262
Figure 51 Write Timing Re-Sequencing Memory ..................................................................... 262
Figure 52 Read Timing for Chunk Buffer Memory ................................................................... 263
Figure 53 Write Timing for Chunk Buffer Memory ................................................................... 263
Figure 54 Read Followed by Write Timing for ZBT Mode........................................................ 264
Figure 55 Read Followed by Write Timing for Standard SSRAM Mode .................................. 264
Figure 56 Read and Write to Non-burstable Register Space................................................... 265
Figure 57 Read and Write to Burstable Address Space .......................................................... 265
Figure 58 Consecutive Write Accesses Using WRDONEB ..................................................... 266
Figure 59 SBI336 Drop Bus Input Interface Timing ................................................................. 272
Figure 60 SBI336 Add Bus Input Interface Timing................................................................... 273
Figure 61 SBI336 Add Bus Output Interface Timing................................................................ 274
Figure 62 SBI ADD BUS Collision Avoidance Timing.............................................................. 274
Figure 63 Receive Any-PHY Interface Timing ......................................................................... 276
Figure 64 Transmit Any-PHY Interface Timing ........................................................................ 277
Figure 65 Synchronous I/O Timing .......................................................................................... 278
Figure 66 JTAG Port Interface Timing ..................................................................................... 279
SSRAM ................................................................................................................................. 84
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
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