PM7312 pmc-sierra, PM7312 Datasheet - Page 38

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
Pin Name
RSX
RSOP
REOP
Type
Tristate
Output
Tristate
Output
Tristate
Output
Pin No.
Y2
Y1
W5
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Function
calculated over the RXDATA[15:0] signals (regardless of RMOD
state). RXPRTY is driven/tristated at the same time as
RXDATA[15:0].
Any-PHY Level 3 Mode:
The receive parity signal (RXPRTY) reflects the odd parity
calculated over the RXDATA[7:0] signals. RXPRTY is valid when
RXDATA[7:0] is valid.
Regardless of mode, RXPRTY is updated on the rising edge of
RXCLK.
The receive start of transfer signal (RSX) denotes the start of data
transfer on the receive APPI.
RSX is updated on the rising edge of RXCLK.
Any-PHY Level 2 Mode
When the RSX signal is set high, the data on the RXDATA[15:0]
signals contains the address that identifies the device and channel
associated with the data to follow. When the RSX signal is sampled
low, the word on the RXDATA[15:0] signals does not contain a
channel address.
RSX is tristated when the FREEDM 32A1024L device is not
selected via the RENB signal.
RSX is updated on the rising edge of RXCLK.
It is recommended that RSX be connected externally to a weak
pull-down, e.g. 10 kW.
Any-PHY Level 3 Mode
When the RSX signal is set high, the data on the RXDATA[7:0]
signals contains the most significant byte of the address that
identifies the device and channel associated with the data to follow.
When the RSX signal is sampled low, the byte on the RXDATA[7:0]
signals does not contain the first byte of the channel address.
Receive Start of Packet.
Marks the cycle containing the start of the packet. The FREEDM
32A1024L drives RSOP high at the start of a packet in a transfer
period and holds RSOP low afterwards. RSOP is used when
supporting both Any-PHY Level 2 and 3 operating modes.
Any-PHY Level 2 Mode:
RSOP is driven high one clock cycle after the RSX is driven high.
RSOP is tri-stated after the last word of the packet is sent.
Any-PHY Level 3 Mode:
RSOP is driven high two clock cycles after the RSX is driven high.
RSOP is tri-stated after the last byte of the packet is sent.
Note – When an Any-PHY channel is operating in ‘cut-through’
mode (CUT_THRU bits in RFRAG memory set to non-zero value),
RSOP is asserted at the beginning of every partial packet created
by the RFRAG block, whether or not that partial packet
corresponds to the start of a real packet.
The receive end of packet signal (REOP) denotes the end of a
packet. REOP is only valid during data transfer.
REOP is updated on the rising edge of RXCLK.
Any-PHY Level 2 Mode:
When REOP is set high, RXDATA[15:0] contains the last data byte
of a packet. When REOP is set low, RXDATA[15:0] does not
Released
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