PM7312 pmc-sierra, PM7312 Datasheet - Page 262

• Manufacturer Part Number: PM7312
• Description: Freedm 32a1024l Assp Telecom Standard Datasheet
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2021833, Issue 2
14.7 Re-Sequencing SDRAM Interface
When supporting Any-PHY Level 3 mode polling is completely decoupled from data transfer on the
Tx APPI (Figure 49) with the restriction that the TPA poll result is invalid for all channels if it
corresponds to a TXADDR poll coincident with the start of transfer (i.e. the cycle in which TSX is
driven high). Accordingly, the TXADDR[15:0] signals continue to provide only a poll address for
the FREEDM 32A1024L device The FREEDM 32A1024L compares the TXADDR[15:0] to the
base and range address registers to determine if the Any-PHY channel being polled resides within
the device. Poll results are returned on the TPA signal. The meaning of the TPA responses depends
on the setting of the TPA_MODE bit in the TFRAG Any-PHY Channel RAM. The user may
configure TPA_HI/TPA_LO to report whether or not space exists in the Any-PHY channel FIFO to
accept a further MTU-sized packet. Alternatively, TPA_HI/ TPA_LO may be configured to report
whether the FIFO fill level is above or below a user-defined threshold.
The following two diagrams depict the timing for signals destined for the pins of the Re-sequencing
SDRAM during the Activate-Read (with Auto-precharge), and Activate-Write (with Auto-precharge
sequences.
Figure 50 Read Timing for Re-Sequencing Memory
Figure 51 Write Timing Re-Sequencing Memory
RSADD[12:0]
RSDAT[31:0]
RSADD[12:0]
RSDAT[47:0]
RSADD[10]
RSADD[10]
RSBS[1:0]
RSBS[1:0]
RSRASB
RSCASB
RSRASB
RSCASB
SYSCLK
SYSCLK
RSWEB
RSWEB
RSCSB
RSCSB
ROW ADDR
BANK ADDR
ROW ADDR
ROW ADDR
BANK ADDR
ROW ADDR
FREEDM 32A1024L ASSP Telecom Standard Product Data Sheet
Dis Auto Prech
COL ADDR0
BANK ADDR
COL ADDR
BANK ADDR
WR_W0
Dis Auto Pre
Dis. Auto PrechEn. Auto Prech
COL_ADDR1 COL_ADDR2
BANK ADDR BANK ADDR
RD_W0
COL ADDR
BANK ADDR
WR_W1
Dis Auto Pre
RD_W1
COL ADDR
BANK ADDR
WR_W2
En Auto Pre
RD_W2
Released
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