CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 97

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
12. FIQ Interrupt Logic
The FIQ Interrupt Logic selects one out of eight interrupt
sources as the CPU’s nFIQ input. An interrupt request is
latched in a pending flag until it is cleared by SW. The output
can be disabled.
12.1. Functional Description
Fig. 12–1:
At one time, only one interrupt source can be connected to
the nFIQ input of the CPU. The interrupt source which is con-
nected to the nFIQ, is disconnected from the corresponding
ISN. This ISN can then be used by SW.
12.2. Registers
P
r/w1:
r/w0:
Micronas
r/w
PRF
CRF.SEL
x
x
7
FIQ0
FIQ1
FIQ2
FIQ3
FIQ4
FIQ5
FIQ6
FIQ7
Block Diagram FIQ
x
6
x
FIQ Pending
Pending FIQ.
No pending FIQ.
Pending Register FIQ
x
x
5
x
4
x
x
x
Interrupt Sources
3
to ISNs
x
2
x
x
x
1
June 12, 2003; 6251-579-1PD
P
0
0
Res
0
1
Features
– Expanding nFIQ input of ARM7TDMI
– 1 of 8 selection
– IRQ or FIQ selectable
Fig. 12–2:
Figure 12–2 shows the reset structure. Registers can’t be
written until the FIQ flag in the standby register SR1 is set.
This Flag is set by HW and SW. It must be cleared by SW
before re-enabling FIQ by bit F in the core’s CPSR register,
or no further interrupt can occur.
reset
r/w
CRF
GE
0
7
Reset Structure
x
x
6
SR1.FIQ
R Q
Control Register FIQ
DB
DB
x
x
5
x
x
4
D Q
S
D
reset CRF
Q
CDC 32xxG-C
CRF.GE
CRF.P
0
3
0
2
SEL
&
0
1
0
0
nFIQ
Res
95