CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 49

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
With the Baud Rate set to 19.23kBaud, f
153.84kHz. With this setting, PLL and ERM jitter consume
2*15ns/19.5us=0.15%
of the tolerable transmitter frequency offset and reduce TOL
only slightly to 1.605%.
4.7.3.2. CAN
The CAN Module contains logic that re-synchronizes a
receiver to a transmitter several times during a telegram. By
these means, a receiver is able to adapt to the transmitter
frequency within narrow limits.
Two situations have to be distinguished:
1. Bit stuffing guarantees a maximum of 10 bit periods
between two consecutive re-synchronization edges. There-
fore the accumulated phase error must be less than the pro-
grammed re-synchronization jump width (SJW). The limita-
tion that this situation imposes on the maximum TOL can be
expressed as:
or
2. Another limit on the maximum TOL is set by the situation
where the CAN logic must be able to correctly sample the
first bit after an error frame. This is the 13th bit after the last
re-synchronization. This limitation can be expressed as:
or
Example (f
With the Baud rate set to 1MBd, t
divided into 10 time quants (t
programmed to 3 t
reserved for the propagation delay segment. In the first case
the maximum tolerance TOL is 1.5% (edge to edge):
In the second case, TOL is 1.2% (edge to sample point):
The smaller value of the above (1.2%) is relevant.
Following the UART example, PLL/ERM jitter consumes up
to 2*15ns of 300ns (SJW = 3 time quants). This makes 30ns/
300ns=10% of this tolerance, thus reducing TOL to 1.08%.
With the Baud rate set to 500kBd, t
The maximum tolerance TOL of 1.2% reduces by 2*15ns/
600ns=5% to 1.14%.
Micronas
0
2 TOL
= 10MHz)
TOL
TOL
TOL
Q
2 TOL
TOL
min t
--------------------------------------------------------------- -
---------------------------------------- -
2
2
(= t
-------------------------- -
2 10 10
min t
--------------------------------------------------------------- -
Phase Seg1
13 10 3
13 t
13 t
Phase Seg1
3
---------------------------- -
2 10 t
Phase Seg1
Q
3
= 100ns). t
Bit
Bit
-------------------
10 t
t
SJW
t
–
SJW
–
–
=
t
t
t
Phase Seg2
Phase Seg2
= t
Phase Seg2
Bit
Bit
0,015
Bit
t
Bit
=
Phase Seg2
Phase Seg2
=2 s and t
0,012
equals 1 s and is
SJW
SAMPLE
and t
). 3 t
TSEG2
June 12, 2003; 6251-579-1PD
Q
=200ns.
equals
Q
are
are
Example (f
With the Baud rate set to 1MBd, t
divided into 8 time quants (t
programmed to 2 t
reserved for the propagation delay segment. In the first case
the maximum tolerance TOL is 1.25% (edge to edge):
In the second case, TOL is 0.98% (edge to sample point):
The smaller value of the above (0.98%) is relevant.
Following the UART example, PLL/ERM jitter consumes up
to 2*15ns of 250ns (SJW = 2 time quants). This gives 30ns/
250ns=12% of this tolerance, thus reducing TOL to 0.86%.
With the Baud rate set to 500kBd, t
The maximum tolerance TOL of 0.98% reduces by 2*15ns/
500ns=6.0% to 0.92%.
4.7.3.3. DIGITbus
The DIGITbus master synchronizes with external devices via
the serial data line. The slave node recovers the transmis-
sion clock from the data signal via an own PLL. This PLL will
lock to the long-term average frequency of the master, and
the slave node sees PLL/ERM jitter as a short-term fre-
quency offset.
Following the UART example, one can define the tolerable
frequency offset:
Every bit starts with a rising edge and thus every bit has a re-
synchronization point. The bit period (t
equal length parts. Falling edges happen nominally after 1/4,
2/4 or 3/4 of the bit period. After 4/4 of the bit period a rising
edge indicates the beginning of the next bit. The DIGITbus
logic tolerates a jitter of these edges up to 1/8 of the bit
period. Thus, a transmitter frequency offset is tolerable up to
f
Again following the UART example, ERM/PLL jitter influ-
ences this tolerable offset:
With the Baud rate set to 31.25kBd, 1/8 of the bit period is
4 s. PLL/ERM jitter reduces the maximum tolerance TOL of
4.7.3.4. SPI and I2C
Modules like SPI and I2C synchronize with external devices
by the serial clock. Thus, no frequency offset between trans-
mitting and receiving station can develop, and no adverse
effects of PLL/ERM operation are expected.
Trans
6.25% by 2*15ns/4 s=0.75% to 6.2%.
= f
Rec
0
1 1/8) = f
= 8MHz)
TOL
TOL
Q
------------------------------------- -
2
Rec
(= t
----------------------- -
2 10 8
Phase Seg1
13 8 2
12.5% and TOL = 6.25%.
2
Q
2
= 125ns). t
CDC 32xxG-C
–
=
0,0125
= t
=
Bit
Bit
Bit
Phase Seg2
0,0098
=2 s and t
) is divided into four
SJW
equals 1 s and is
and t
). 3 t
TSEG2
Q
=250ns.
Q
are
are
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