CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 113

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
15.7. Registers
EOC
r1:
r0:
EOC is reset by a write access to the register AD0. EOC
must be true before starting the first conversion after
enabling the module by setting SR0.ADC.
TSAMP
TSAMP adjusts the sample conversion times.
Table 15–2:
REF
w0:
w1:
w2:
w3:
CHANNEL
CHANNEL selects from which pin of port P0 or P1 the con-
version is done. The MSB of CHANNEL is bit 3.
Table 15–3:
AN 9 to 0
The 10-bit data format is positive integer, i.e. 000H for lowest
and 3FFH for highest possible input signal. The 8 MSB can
be read from register AD1. The two LSB can be read from
Micronas
TSAMP
0H
1H
2H
3H
CHANNEL
0 to 7
8 to 15
w
w
AD0
AD1
r
r
EOC
AN9
0
x
7
7
TSAMP
AN8
x
0
x
6
6
Analog Value Bit 9 to 0
End of Conversion
End of conversion
Busy
Sampling Time
Conversion Reference
External reference from VREF pin used
Internal reference on VREFINT pin used
External reference from VREF0 pin used
External reference from VREF1 pin used
Channel of Input Multiplexer
TSAMP Usage: Sample and Conversion Time
CHANNEL Usage: ADC Input Selection
AN7
ADC Register 0
ADC Register 1
x
0
x
5
5
REF
Port Pin
P0.0 to P0.7
P1.0 to P1.7
t
20/f
60/f
140/f
300/f
AN6
Sample
x
0
x
4
4
0
0
0
0
AN5
x
0
x
3
3
TEST
AN4
CHANNEL
0
x
2
2
t
40/f
80/f
160/f
320/f
Conversion
AN1
AN3
0
x
1
1
0
0
0
0
June 12, 2003; 6251-579-1PD
AN0
AN2
BUF
0
0
0
0
Res
Res
register AD0. The result is available until a new conversion is
started.
BUF
w1:
w0:
TEST
EP06
r/w1:
r/w0:
P06
r1:
r0:
WAIT
r1:
r0:
BVE
r1:
r0:
w1:
w0:
r/w
ANAA
EP06
0
7
P06
6
Input Buffer Usage
Buffer used
Buffer bypassed
for factory use only
Enable P06 Comparator Interrupt Source
output
Enabled.
Disabled.
P06 Comparator Output
P0.6 is lower than AVDD/2.
P0.6 is higher than AVDD/2.
WAIT Comparator Output
WAIT is lower than VREFINT.
WAIT is higher than VREFINT.
BVDD Regulator Error Flag
Out of specification.
Normal operation.
Reset flag.
No action.
WAIT
Analog AVDD Register
5
x
4
CDC 32xxG-C
x
3
x
2
x
1
BVE
0
0
111
Res