CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 131

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CDC3205G-C

Manufacturer Part Number
CDC3205G-C
Description
Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
Manufacturer
Micronas
Datasheet
PRELIMINARY DATA SHEET
20. Stepper Motor Module SV (SMV)
The SMV module serves to control air cored movements or
stepper motors that are directly coupled in H-bridge forma-
tion to H-Ports. Upon CPU programming it creates all wave-
forms necessary to position the drive pointer as desired. In
addition it supports the Rotor Zero Position Detection by sup-
plying motor blockage information.
The Rotor Zero Position Detection capability is protected by
a patent from Siemens VDO Automotive (SV) and may only
be used with SV’s prior approval.
The number of motors that are controllable by subunits (con-
trol units) of the module is given in Table 20–1.
20.1. Principle of Operation
20.1.1. General
An 8-bit, free-running counter FRC (Fig. 20–1) operates on
the f
counter word that is fed to a number of control units SMx.
A control unit (Fig. 20–1) contains 8-bit sine and cosine com-
pare registers. One comparator each is associated with
these registers and creates a compare signal when register
content and FRC word are equal. An output flip-flop associ-
ated with each comparator is set when the FRC word is zero
and reset by the respective compare signal. A delay stage
associated with each control unit delays the flip-flop output
signals by a fixed number of f
chronism between the output signals of the various control
units, thus achieving an improved EMC behavior of the SMV
(cf. Fig. 20–3). According to the setting of a quadrant register
associated with each control unit, each of a unit’s two output
signals is multiplexed to signals SMxn+ and SMxn- so as to
properly control 2 individual H-Ports that form an H-bridge
together with the connected motor coil. By these means, a
control unit supplies two H-bridges with signals SMx1+,
SMx1-, SMx2+ and SMx2- to function as variable pulse width
modulator outputs with selectable polarity.
Summing up: when the compare registers are set to the sine
and cosine value of a desired rotor angle and the quadrant
register is set to the desired quadrant, an air cored move-
ment or a stepper motor connected to the unit’s 4 H-Ports
will carry the proper average coil currents of proper polarity
so that its rotor will assume the desired rotary angle.
Three registers control readjustment of a rotor to a new
angle. Sine, cosine and unit/quadrant registers serve as tem-
porary storage of new sine, cosine, related quadrant and unit
selection values. A scheduler logic times the synchronous
downloading of the three buffered words to the respective
unit’s sine, cosine and quadrant registers, so as to avoid
inconsistencies among them. A Busy bit may be read out sig-
naling completion of the downloading.
Each control unit contains circuitry to detect an induced volt-
age resulting from the rotation of the connected motor’s rotor
(Fig. 20–2). A comparator compares the input voltage from
one of the unit’s H-Ports to 1/9th of the supply voltage. A
capture logic opens a capture window and samples the com-
parator output. The capture result signal supplies a rotor
blockage information necessary for the Rotor Zero Position
Detection in all cases where the CPU has lost track of the
Micronas
SM
input clock (generally 4MHz) and creates an 8-bit
SM
cycles to achieve non-syn-
June 12, 2003; 6251-579-1PD
Features
– Multi channel pulse width modulated output
– Outputs offset for improved EMC properties
– Four quadrant operation
– 8-bit resolution
– Analog voltage sampling for Rotor Zero Position Detection
– HW Option selectable output cycle frequency
display angle of a pointer that is driven by the motor via a
mechanical transmission.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
20.1.2. Hardware settings
Prior to entering active mode, the f
set by HW Option (see Table 20–1 on page 130). A fre-
quency value of 4MHz is recommended resulting in a pulse
width modulator cycle frequency of 4MHz/256. Furthermore,
the Rotor Zero Position Detection clock has to be set by HW
Option (see Table 20–1 on page 130).
Some H-Ports may receive the output signals either of the
SMV module or of PWM modules as an alternative. Refer to
Table 20–1 for the necessary settings.
Refer to section “HW Options” for details.
20.1.3. Initialization
Prior to entering active mode, proper SW initialization of the
H-Ports assigned to function as H-bridge outputs SMxn+ and
SMxn- has to be made (Table 20–1). The H-Ports have to be
configured Special Out. Refer to “Ports” for details.
20.1.4. Operation
After reset, the SMV is in standby mode (inactive). The out-
put lines to the H-Ports are low.
For entering active mode, set bit SR0.SM. The FRC will
immediately start counting but the control units’ output lines
will still be low.
20.1.4.1. Generating Output
After entering active mode, the SMV’s control units are ready
to receive sine, cosine and quadrant values.
First load the unit/quadrant information to register SMVC,
then the cosine value to register SMVCOS and last the sine
value to register SMVSIN. Upon writing SMVSIN, the sched-
uler logic will set flag SMVSIN.BUSY and load the buffered
selectable for all H-bridge outputs
CDC 32xxG-C
SM
input clock has to be
129

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