CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 155

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
24.1.4. Operation
24.1.4.1. Transmit Mode
Transmission is initiated by a write access to data register
SPIxD. The SPI will immediately begin transmitting the
selected number of data bits out from its shift register, in syn-
chronism with the selected clock. A write access during a
transmission is ignored. The frame is transmitted MSB first.
In nine-bit mode flag BIT8 is MSB of the shift register (Fig.
24–2 to 24–5). At the end of the frame, an interrupt source
signal is generated which may be selected to trigger an inter-
rupt.
24.1.4.2. Receive Mode
The receive mode must be activated by a write access to
register SPIxD. The SPI will immediately begin clocking in
the selected number of data bits into its shift register, in syn-
chronism with the selected clock. At the end of the frame, an
interrupt source signal is generated which may be selected
to trigger an interrupt.
24.1.4.3. DMA
Please refer to section “DMA” for information about operation
of the SPI in DMA mode.
24.2. Registers
The following registers are available once for SPI0 and SPI1
each.
BIT8
r/w:
In 8 bit mode (LEN9 = 0) this bit is undefined when read.
LEN9
r/w0:
r/w1:
RXSEL
r/w0:
r/w1:
INTERN
r/w0:
r/w1:
Micronas
r/w
r/w
SPIxD
SPIxM
BIT8
0
0
7
7
LEN9
0
0
6
6
Bit 8 of Rx/Tx Data
Use external clock.
Rx/Tx data bit.
Frame Length 9 Bit Selection
8 bit mode.
9 bit mode.
Receive Selection
Input active.
Low level at input.
Internal/External Clock Selection
Use internal clock.
RXSEL INTERN
SPI x Data Register
SPI x Mode Register
0
0
5
5
Bit 7 to 0 of Rx/Tx Data
0
0
4
4
0
0
3
3
SCLK
0
0
2
2
0
0
1
1
CSF
June 12, 2003; 6251-579-1PD
0
0
0
0
Res
Res
24.1.5. Inactivation
Returning a SPI module to standby mode by resetting its
respective enable bit (Table 24–1) will immediately terminate
any running receive or transmit operation and will reset all
internal registers.
24.1.6. Precautions
A single wire bus is easiest implemented by a wired-or con-
figuration of the SPIx-D-OUT output port and the open drain
output of the external transmitter:
simply configure the SPIx-D-OUT output port in Port Slow
mode, always operate it in Port Special Output mode and
connect it directly to the external open drain output. An exter-
nal pull-up resistor is not necessary in this configuration
because the SPIx-D-OUT output port supplies the necessary
pull-up drive.
If the SPIx-D-OUT output port has to be operated in Port
Fast mode, this simple scheme is not possible, because the
pull-down action of the external open drain output may
exceed the absolute maximum current rating of the SPIx-D-
OUT output port. A discrete external wired-or is recom-
mended for this situation.
During operation, make sure, that the external clock does not
start until after SPIxD has been written, otherwise correct
data transfer is not be guaranteed.
SCLK
r/w:
Table 24–2:
CSF
w:
Table 24–3:
SCLK
1
0
0
1
1
CSF
1
0
0
1
0
0
1
0
1
0
0
1
x
Clock
Polarity
low
high
Source of internal clock
F0SPI
F1SPI
F2SPI
Sample Clock
Clock polarity and edge of data sampling.
(Table 24–2)
Clock Selection Field
Source of internal clock (Table 24–3)
SCLK usage
CSF usage
Sampling
Edge
falling
rising
rising
falling
CDC 32xxG-C
See Fig.
24–3
24–5
24–2
24–4
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