CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 137

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
21. LCD Module
The Liquid Crystal Display (LCD) Module is designed to
directly drive a 1:4 multiplexed liquid crystal display. It gener-
ates all signals necessary to drive 4 backplane and 48 seg-
ment lines which are output via U-Ports in LCD mode. Up to
192 segments or pixels can be controlled if all U-Ports are
designated as segment outputs.
In addition, the module provides functions that enable the
user to cascade it with external expansion ICs providing
more segment lines. It can be operated as master or slave in
such an extended system.
21.1. Principle of Operation
21.1.1. General
Each LCD pixel or segment which is controlled by the LCD
module is located at the crossing point of a segment line and
a backplane line. The LCD module co-ordinates the output
sequences of backplane and segment lines (see Fig. 21–3
on page 137).
Fig. 21–1:
A segment pin can drive 4 different voltage levels (UVSS, 1/3
UVDD, 2/3 UVDD, UVDD) in LCD mode. The output of each
segment pin is controlled by the corresponding segment bits
of the registers UxD, UxTRI, UxNS and UxDPM (further
called segment registers). Each such register contains one
bit (of a 4 bit segment field) for each of its port pins. Each
segment bit (0 to 3) of a segment field corresponds to a
backplane line (BP0 to BP3). If the segment bit, correspond-
ing with the backplane line BPx is true, then the segment at
the crossing of the two lines is on (black).
The LCD module does not contain a display ROM translating
character information into segment code. The advantage is
that arbitrary characters or displays can be generated just by
changing the program code. Segment information is directly
entered by writing to the corresponding segment bit. It is val-
idated (loaded to all corresponding slave registers) for all
segment U-Ports simultaneously by a write access to regis-
ter ULCDLD.
Two internal voltage sources provide the U-Port circuits and
the backplane generator with the voltage levels 1/3 UVDD
and 2/3 UVDD. These levels are generated by a buffered
resistor divider.
Micronas
SEGn-1
SEGn
SEGn+1
Segments and Backplanes
BP3
BP2
BP1
BP0
June 12, 2003; 6251-579-1PD
Features
– 1:4 multiplex
– 5V supply
– Maximum of 192 segments
– Cascadable with external expansion ICs
– 0.3mA buffered 1/3 and 2/3 voltage divider
– Zero standby current
– 200 A no load active current
– Frame frequency HW Option selectable
21.1.2. Hardware settings
The LCD frame frequency is settable by HW option LC. The
resulting frame frequency is the selected input frequency,
divided by 120. It should be in the range from 50 to 200Hz.
For best electromagnetic interference results it is recom-
mended to operate all segment and backplane U-Ports in
Port Slow mode. Refer to “Ports” for more details and to
“HW-Options” for setting the corresponding HW options. Set
flag PSLW in register SR0 to HIGH to enable Port Slow
mode.
21.1.3. Initialization
After reset, the LCD module is in standby mode (inactive)
and all U-Ports are in Port mode, non-conducting.
All U-Ports designated to function as backplane or segment
outputs are to be set to LCD mode. Refer to “Ports” for more
details. This will set these U-Ports to output LOW state.
After reset the content of the segment registers is undefined.
It must be set by writing the desired segment information to
the segment registers and by validating it by a write access
to register ULCDLD (write 0x00 for master mode, 0xFF for
slave mode), before the LCD module is enabled.
21.1.4. Operation
For entering active mode, set flag LCD in register SR0. Each
segment and backplane U-Port will immediately start produc-
ing its LCD output signal according to the segment informa-
tion provided during initialization.
During active mode, a new segment information is entered
by simply writing the desired segment information to the seg-
ment registers and by validating it by a write access to regis-
ter ULCDLD (write 0x00 while in master mode, 0xFF while in
slave mode). Each segment and backplane U-Port will imme-
diately start producing an LCD output signal according to the
new segment information.
Returning the LCD module to standby mode by resetting flag
LCD in register SR0 will immediately return all segment and
backplane U-Ports to the output LOW state.
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