SDA6000 Micronas, SDA6000 Datasheet
SDA6000
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SDA6000 Summary of contents
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Edition March 1, 2001 6251-557-1 USER’S MANUAL SDA 6000 Teletext Decoder with Embedded 16-bit Controller M2 ...
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... Complete Update of Controller & Peripheral Spec --> Detailed Version ASC: Autobaud Detection Feature included IC: New Description GPT: New Description 2 IIC changed For questions on technology, delivery and prices please contact the Micronas Offices in Germany or the Micronas GmbH Companies and Representatives worldwide: see our webpage at http://www.micronas.com ...
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Contents Overview ...
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... Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . 5.2.2 Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . 5.2.3 Interrupt Response Times 5.2.4 PEC Response Times 5.2.5 Fast Interrupts 5.3 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 External Interrupt Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . System Control & Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . A PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.3.1 Baud Rates in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . 7.3.3.2 Baud Rates in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . 7.3.4 Autobaud Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.4.1 Serial Frames for Autobaud Detection . . . . . . . . . . . . . . . . . . . . . A-4 PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Screen Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Layer Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Overlapped Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Embedded Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Transparency in Screen Background Area . . . . . . . . . . . . . . . . . . . 10.4 Input and Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Initialization of Memory Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... Recommended Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . Register Overview 13.1 Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 CPU General Purpose Registers (GPRs) 13.3 Registers ordered by Context 13.4 Registers Ordered by Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 Registers in SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Registers in ESFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 PRELIMINARY DATA SHEET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Version 2.1 Micronas ...
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... SDA 6000 14.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... Evaluation of the Incremental Encoder Signals . . . . . . . . . . . . . . . Figure 7-9 Block Diagram of an Auxiliary Timer in Counter Mode . . . . . . . . . Figure 7-10 Concatenation of Core Timer T3 and an Auxiliary Timer . . . . . . . . Figure 7-11 GPT1 Auxiliary Timer in Reload Mode Figure 7-12 GPT1 Timer Reload Configuration for PWM Generation . . . . . . . . B-1 PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... SFRs and Port Pins Associated with the A/D Converter . . . . . . . 7 - 118 Figure 8-1 Clock System Figure 9-1 M2’s Display Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9-2 Priority of Clamp Phase, Screen Background and Pixel Layer Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-1 Display Regions and Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... Figure 10-21 Organization of GAIs in the External SDRAM . . . . . . . . . . . . . . . Figure 10-22 GAI Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-1 Block Diagram of Digital Slicer and Acquisition Interface . . . . . . . Figure 12-2 VBI Buffer: General Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14-1 H/V - Sync-Timing (Sync-master mode Figure 14-2 VCS -Timing (Sync-master mode B-3 PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... Chapter 12, Acquisition and Slicer Describes features and functionality of the data caption unit. • Chapter 13, Register Overview Summarizes all HW-registers of M2. • Chapter 14, Electrical Characteristics Lists all important AC and DC values and the maximum operating conditions of M2. C-1 PRELIMINARY DATA SHEET Version 2.1 Micronas ...
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... For easier understanding of this specification it is recommended to read the documentation listed in the following table. Moreover it gives an overview of the software drivers which are available for M2. Document Name Appl. Note “Initialization and Bootstraploader of M2” C-2 PRELIMINARY DATA SHEET Document Purpose System integration support Version 2.1 Micronas ...
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... The memory architecture is based on the concept of a unified memory - placing program code, variables, application data, bitmaps and data captured from the analog TV signal’s vertical blanking interval (VBI) in the same physical memory. M2’s external bus interface PRELIMINARY DATA SHEET Version 2.1 Overview Micronas ...
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... Verification and validation before targeting • General test concept • Documentation • Graphical interface design for non-programmers • Modular and open tool chain, configurable by customer MATE uses available C166 microcontroller family standard tools as well as a dedicated M2 tools PRELIMINARY DATA SHEET Version 2.1 Overview Micronas ...
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... Embedded System the 16 Bit MC, TTX/EPG/TeleWeb, High End OSD Engine Figure 1-1 M2 Tool Flow PRELIMINARY DATA SHEET New Tool Generation User Interface Simulator C Compiler Object Code C166-Available Linker/Locator PC Simulator + EVA Board Version 2.1 Overview Events and Action Editor C Code Generator C Sources Debugging UEB11114 Micronas ...
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... Evaluation Board Simulator to connect a C166 EVA Board to the M2 simulation The M2 software is written in ANSI-C to fulfil the platform independent development. The ported software is code and runtime optimized. The layers of the modular architecture are separated by application program interfaces which ensure independent handling of the modules PRELIMINARY DATA SHEET Version 2.1 Overview Micronas ...
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... KBytes XRAM On-chip • General Purpose Timer Units (GPT1 and GPT2). • Asynchronous/Synchronous Serial Interface (ASC0) with IrDA Support. Full-duplex Asynchronous MBaud or Half-duplex Synchronous up to 4.1 MBaud. Type SDA 6000 PRELIMINARY DATA SHEET P-MQFP-128-2 Package P-MQFP-128-2 Version 2.1 Overview CMOS Micronas ...
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... Full Channel Data Slicing Supported • Fully Digital Signal Processing • Noise Measurement and Controlled Noise Compensation • Attenuation Measurement and Compensation • Group Delay Measurement and Compensation • Exact Decoding of Echo Disturbed Signals PRELIMINARY DATA SHEET Version 2.1 Overview 2 C Channels at 400 Kbit/s Micronas ...
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... UDQM LDQM CLKEN Figure 1-2 Logic Symbol DD(3 DD(2.5 V) PRELIMINARY DATA SHEET Version 2.1 Overview Address 16 Bit Data 16 Bit Port 2 8 Bit Port 3 15 Bit Port 4 6 Bit Port 5 6 Bit Port 6 7 Bit JTAG 4 Bit UEL11115 Micronas ...
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Pin Description ...
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... SDA 6000 2 Pin Descriptions PRELIMINARY DATA SHEET Version 2.1 Pin Descriptions Micronas ...
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... Pin Descriptions D13 V 61 DD33 SS33 D14 DD33 SS33-4 51 D15 LDQM 48 UDQM CSROM 45 CLKEN 44 CSSDRAM 43 MEMCLK V 42 DD33 SS33-3 40 A15/CAS 39 A14/RAS 38 A13 UEP11116 Micronas ...
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... Address bit/SDRAM address bit O Address bit/ Row address strobe for SDRAM access O Address bit/ Column address strobe for SDRAM access I/O Data bit I/O Data bit I/O Data bit I/O Data bit I/O Data bit I/O Data bit I/O Data bit I/O Data bit I/O Data bit I/O Data bit Version 2.1 Pin Descriptions Micronas ...
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... Output of the oscillator amplifier circuit I Input of the oscillator amplifier circuit I Reset input pin I CVBS signal inputs for full service data slicing I Ground for CVBS1A (differential input) I CVBS signal inputs for WSS data slicing O Analog output for red channel Version 2.1 Pin Descriptions Micronas ...
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... General purpose I/O port/GPT1 timer T3 ext. up/down I/O General purpose I/O port/GPT1 timer T4 input for count/gate/reload/capture I/O General purpose I/O port/GPT1 timer T3 count/gate input I/O General purpose I/O port/GPT1 timer T2 input for count/gate/reload/capture I/O General purpose I/O port/SSC master- receiver/slave-transmit I/O Version 2.1 Pin Descriptions 2 C Bus clock line Bus data line 0 Micronas ...
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... Chip Debug System’ (OCDS) I/O General purpose I/O port I/O General purpose I/O port/I I/O General purpose I/O port/I I/O General purpose I/O port I/O General purpose I/O port/I I Clock for JTAG interface I Data input for JTAG interface Version 2.1 Pin Descriptions 2 C bus clock line bus data line bus data line 2 Micronas ...
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... Testmode pin S Analog ground S Analog power (for PLL and DAC) (2 Analog ground S Analog power (for ADCs) (2 Digital ground (for digital core) S Digital power (for digital core) (2 Digital ground for pads S Digital power (for pads) (3.3 V) Version 2.1 Pin Descriptions Micronas ...
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Architectural Overview ...
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... SDA 6000 3 Architectural Overview AMI Figure 3-1 M2 Top Level Block Diagram PRELIMINARY DATA SHEET Version 2.1 Architectural Overview Micronas ...
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... M2 supports two hardware display layers. To refresh the screen the M2 reads and mixes two independent pixel sources simultaneously. Different formats of the pixels which are part of different applications (e.g. Teletext formats, 12-bit RGB or 16-bit RGB values) can be stored in the same frame buffer at the same time PRELIMINARY DATA SHEET Version 2.1 Architectural Overview Micronas ...
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... MBit organized as 4 memory banks). For TV controlling tasks M2 provides three serial interfaces (I purpose timers, (GPT1, GPT2), a real time clock (RTC), a watch dog timer (WDT converter and eight external interrupts PRELIMINARY DATA SHEET Version 2.1 Architectural Overview 2 C, ASC, SSC), two general Micronas ...
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C16X Microcontroller ...
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... SDA 6000 4 C16X Microcontroller PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... Its main features are the following: • 4-stage pipeline (Fetch, Decode, Execute and Write-Back). • 16 ⌠ 16-bit General Purpose Registers • 16-bit Arithmetic and Logic Unit • Barrel shifter • Bit processing capability PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... Watchdog timer module • General XBUS peripherals control • Power management additional to the standard Idle and Power Down modes • Control interface for Clock Generation Unit • Identification register block for chip and CSCU identification PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... The On-Chip Debug System allows the detection of specific events during user program execution through software and hardware breakpoints. An additional communication module allows communication between the OCDS and an external debugger, through a standard JTAG port. This communication is performed in parallel to program execution PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... In case of cache miss wait states are inserted until the data is ready. IRAM, XRAM and the special function register areas can be accessed without wait states PRELIMINARY DATA SHEET C16X Microcontroller 2 C, internal XBUS memory (XRAM)) and the to 41 (excluding internal memory H H Version 2.1 Micronas ...
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... Bit addressing is supported by a part of the special function registers, a part of the IRAM and the general purpose registers (GPRs Boot ROM ICACHE EBI AMI DCACHE PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller PMBUS C16X XBUS ACQ UED11214 Micronas ...
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... Storage of Words, Byte and Bits in a Byte Organized Memory Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... Figure 4-3 Page Kbyte Page 2 H Page 1 H Page 0 H PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller RAM / SFR Area 4 Kbytes 00’FFFF H SFR Area 00’FE00 H 00’FA00 IRAM H 00’F600 H Reserved 00’F200 H ESFR Area 00’F000 H UED11213 Micronas ...
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... H H 00’FBFE … 00’FB80 H H 00’FBFE … 00’FBC0 H H 00’FBFE … 00’F800 H H Reserved. Do not use this combination. Reserved. Do not use this combination. 00’FDFE … 00’F600 (Note: No circular stack Version 2.1 C16X Microcontroller ) and the GPRs of the Micronas ...
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... CP register. A particular Switch Context (SCXT) instruction performs register bank switching and automatically saves the previous PRELIMINARY DATA SHEET C16X Microcontroller Word Register R15 R14 R13 R12 R11 R10 R9 R8 RL7 R7 RL6 R6 RL5 R5 RL4 R4 RL3 R3 RL2 R2 RL1 R1 RL0 R0 Version 2.1 Micronas ...
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... PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller to 00’FCFE (just below the bit 00’FD00 H 00’FCFE H 00’FCE0 H 00’FDDE H Internal RAM 00’F600 H 00’F5FE H MCD02266 Micronas ...
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... ESFR space ;(EXTR is not required for this access) ;The scope of the EXTR #4 instruction… ; … ends here! ;T8REL uses 16-bit mem address, ;R1 is accessed via the SFR space PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller … 00’F000 ). H H Micronas ...
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... SDA 6000 Note: The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... External Static Memory Devices M2 supports access to external ROM, Flash ROM and SRAM devices which provide a read cycle time t < 120 ns. Only 16-bit word access is supported. The maximum PRELIMINARY DATA SHEET # Bank # Row Addresses Addresses Version 2.1 C16X Microcontroller # Column Addresses 8 8 Micronas ...
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... SDA 6000 memory size is limited by the number of external address lines external address lines are configurable, thus devices providing MByte of static external memory can be connected to M2 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... The first figure presents the interlocked execution of access cycles to the external ROM and a SDRAM device. The other figure resumes the situation when both sources PRELIMINARY DATA SHEET C16X Microcontroller ROM ROM or or Flash-ROM Flash-ROM 128 KByte...4 MByte 128 KByte...4 MByte M2 Version 2.1 UEB11118 Micronas ...
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... SDRAM banks. Detailed timings and the specification of setup and hold conditions can be found in Chapter 14. MEMCLK CSSDRAM RAS Read CAS WR ca A(21:0) SDRAM Data D(15:0) CSROM RD Figure 4-6 Interlocked Access Cycles to ROM and SDRAM PRELIMINARY DATA SHEET C16X Microcontroller Act ra ROM_Adr ROM Data Version 2.1 Write ra UET11119 Micronas ...
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... Bank Bank Activate PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Pre Act Read Precharge Activate UET11120 Micronas ...
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... H H ... 40’FFFF are mapped to 00’8000 H H PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller EBI Address-Space FF’FFFF H D 80’0000 H S2 41’0000 H 40’0000 00’0000 H UED11212 ... H shown to the ICACHE, H ... 01’7FFF : H H ... 00’7FFF H H ... 3F’FFFF H H Micronas ...
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... PRELIMINARY DATA SHEET address mod address – REDIR_LOWER ´ 16 kBytes 80’0000 H address + 40’0000 H ... 40’FFFF H H (9F’FFFF ) access the 64MBit (16 MBit) SDRAM H H ... 7F’FFFF H ... 3F’FFFF H H Version 2.1 C16X Microcontroller ... H (PMBUS) and 41’0000 H are passed to the H must not be used. If the Micronas ...
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... SDRAM such as the execution of the requisite initialization sequence, power down mode entry/exit etc. When executing a direct mode command the EBI shifts the contents of register EBIDIR into the SDRAM control lines. The Micronas SDRAM driver (refer to document list) provides appropriate functions for executing operations in direct mode. 4.5.2 ...
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... EBI PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 00FF REDIR1_SEG (7:0) rw Reset Value: 0000 REF SDR - SZE Micronas ...
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... Control Bit for Pin CSSDRAM in Direct Mode CLKEN Control Bit for Pin CLKEN in Direct Mode CLK - - - - - EN rw PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller II III IV UET11123 Reset Value: 0000 RAS CAS WR ADR _10 Micronas H ...
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... PRELIMINARY DATA SHEET CLKEN CS_N RAS_N CAS_N WE_N ADR_10 Version 2.1 C16X Microcontroller Micronas ...
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... The address space implicitly divided into equally sized blocks of different granularity and into logical memory areas. Crossing the boundaries between these PRELIMINARY DATA SHEET Physical Base Address 2nd ROM device not possible 20’0000 H 10’0000 H 08’0000 H 04’0000 H 02’0000 H Version 2.1 C16X Microcontroller Micronas ...
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... Subsequent 16-bit data addresses that cross the 16 KByte data page boundaries will therefore use different data page pointers, while the physical locations need not be subsequent within memory PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... Instr. Ptr. Bit-Mask Gen Purpose ALU 4-Stage (16-bit) Pipeline Registers Barrel - Shifter PSW SYSCON Context Ptr. BUSCON 0 R0 BUSCON 1 ADDRSEL 1 BUSCON 2 ADDRSEL 2 BUSCON 3 ADDRSEL 3 BUSCON 4 ADDRSEL 4 Code Seg. Ptr. PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller 16 Internal RAM R15 R0 16 MCB02147 Micronas ...
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... The instruction pipeline of the CPU separates instruction processing into four stages, and each one has an individual task PRELIMINARY DATA SHEET C16X Microcontroller SYSCON (RP0H) PSW IP, CSP DPP0, DPP1, DPP2, DPP3 CP SP, STKUN, STKOV MDL, MDH, MDC ZEROS, ONES Version 2.1 Micronas ...
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... Pipelining, however, allows parallel (i.e. simultaneous) processing four instructions. Thus, most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset (see Figure 4-11 PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... Injection n+2 TARGET TARGET BRANCH INJECT TARGET BRANCH n INJECT ... I BRANCH n Version 2.1 C16X Microcontroller UED11124 I I TARGET+2 TARGET TARGET+1 TARGET TARGET TARGET INJECT TARGET UED11125 Micronas ...
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... Target Instruction TARGET TARGET+1 n Cache Jmp INJECT TARGET Cache Jmp INJECT n ... I Cache Jmp n 1st Loop Iteration Repeated Loop Iteration PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller I I TARGET+1 TARGET TARGET TARGET+1 I Cache Jmp TARGET I Cache Jmp n UED11126 Micronas ...
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... GPR ; write to GPR 0 in the new context ; select data page 4 via DPP0 ; must not be an instruction using DPP0 01’0000 H ; (in data page 4) supposed segmentation is enabled ; must not be an instruction popping operands ; from the system stack Version 2.1 C16X Microcontroller Micronas ...
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... Note rule, instructions that change external bus properties should not be executed from the respective external memory area PRELIMINARY DATA SHEET ; pop word value from new top of stack into R0 ; globally disable interrupts ; non-critical instruction ; begin of uninterruptable critical sequence ; end of uninterruptable critical sequence ; globally re-enable interrupts Version 2.1 C16X Microcontroller Micronas ...
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... The solution is either the implemented hardware protection (see below PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... Mux Bus 3 Execution from the internal RAM provides flexibility in terms of loadable and modifiable code on the account of execution time PRELIMINARY DATA SHEET Instruction Fetch Word Operand Access Doubleword Read from Instruction 0 Version 2.1 C16X Microcontroller Write to – Micronas ...
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... Non-implemented (reserved) SFR bits cannot be modified, and will always supply a read value of '0'. System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT4 pins during reset PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... Segmentation Disable/Enable Control ‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit). ‘1’: Segmentation disabled (Only IP is saved/restored CFG PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0400 RSO - XPEN - - Micronas ...
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... This bit-addressable register reflects the current state of the microcontroller. Two groups of bits represent the current ALU status, and the current CPU interrupt status. A separate bit (USR0) within register PSW is provided as a general purpose user flag … 00’7FFF ) H H … 01’7FFF ). H H PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Micronas ...
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... PSW register after execution of the immediately preceding instruction. Note: After reset, all of the ALU status bits are cleared HLD - - - USR0 MUL PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0000 Micronas ...
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... LSB of the result. In conjunction with the ’ to ‘+7F H ’ to ‘+7F ’), otherwise the V-flag is cleared. Note that the H PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller ’ H ’ for the byte data type. For H ’ to ‘+7FFF ’), bits H H Micronas ...
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... PRELIMINARY DATA SHEET Rounding Error Quantity - No rounding error - 1 0 < Rounding error < Rounding error = / 1 Rounding error > / ’ for the word data type, or ‘80 H Version 2.1 C16X Microcontroller LSB 2 LSB 2 LSB 2 ’ for the byte data H Micronas ...
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... This non-bit addressable register selects the code segment being used at run-time to access instructions. The lower 8 bits of register CSP select one 256 segments of 64 KBytes each, while the upper 8 bits are reserved for future use PRELIMINARY DATA SHEET (15..0) r/w Version 2.1 C16X Microcontroller Reset Value: 0000 Micronas ...
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... RETS and RETI instructions. Upon the acceptance of an interrupt or the execution of a software TRAP instruction, the CSP register is automatically set to zero PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0000 SEGNR(7..0) r Micronas ...
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... CSP Register 24/20/18-Bit Physical Code Address DPP0PN DPP1PN rw PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller IP Register 0 MCA02265 Reset Value: 0000 Reset Value: 0001 Micronas ...
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... Port 4 for all external data accesses. A DPP register can be updated via any instruction, which is capable of modifying an SFR DPP2PN DPP3PN rw PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0002 Reset Value: 0003 Micronas ...
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... PRELIMINARY DATA SHEET 16-Bit Data Address 15 14 DPP Registers DPP3-11 DPP2-10 DPP1-01 DPP0- Version 2.1 C16X Microcontroller 0 14-Bit Intra-Page Address (concatenated with content of DPPx). MCA02264 Reset Value: FC00 Micronas ...
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... Figure 4-16 Register Bank Selection via Register CP Several addressing modes use the CP register implicitly for address calculations. The addressing modes mentioned below are described in the “C16x Family Instruction Set Manual” PRELIMINARY DATA SHEET C16X Microcontroller H H Version 2.1 /00’F600 /00’F200 Micronas ...
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... Since the least significant bit of the SP register is tied to ‘0’, and bits 15 through 12 are tied to ‘1’ by hardware, the SP register can only contain values from F000 This allows access to a physical stack within the internal RAM of the M2. A virtual stack PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller FFFE . H H Micronas ...
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... Fatal error indication treats the stack overflow as a system error through the associated trap service routine. Under these circumstances data in the bottom of the PRELIMINARY DATA SHEET stkov rw Version 2.1 C16X Microcontroller Reset Value: FC00 Reset Value: FA00 Micronas ...
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... The stack limit control, realized by the register pair STKOV and STKUN, detects cases where the stack pointer SP is moved outside the defined stack area either by ADD PRELIMINARY DATA SHEET stkun rw Version 2.1 C16X Microcontroller to H Reset Value: FC00 Micronas ...
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... MDL register must be loaded with the low order 16 bits of the 32-bit dividend before the division is started. After any division, the MDL register represents the 16-bit quotient PRELIMINARY DATA SHEET mdh rw Version 2.1 C16X Microcontroller Reset Value: 0000 Micronas ...
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... When division or multiplication is interrupted before its completion and the multiply/divide unit is required, the MDC register must first be saved along with the MDH and MDL PRELIMINARY DATA SHEET mdl MDR - - !! !! !! r(w) r(w) r(w) r(w) Version 2.1 C16X Microcontroller Reset Value: 0000 Reset Value: 0000 r(w) r(w) r(w) r(w) Micronas ...
Page 86
... PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller Reset Value: 0000 Reset Value: FFFF Micronas ...
Page 87
... Device Identification (7 … 0) Identifies the device name. IDMANUF Bit Function MANUF JEDEC Normalized Manufacturer Code 0C1 : Infineon Technologies MANUF r PRELIMINARY DATA SHEET Version 2.1 C16X Microcontroller CHIPREVNU(7..0) r ’ Micronas ...
Page 88
Interrupt and Trap Function ...
Page 89
... Hardware traps always have highest priority and cause immediate system reaction. The software trap function is invoked by the TRAP instruction, which generates a software interrupt for a specified interrupt vector. For all types of traps the current program status is saved on the system stack PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 90
... The mnemonics are composed of a part that specifies the respective source, followed by a part that specifies their function (IR = Interrupt Request flag Interrupt Enable flag PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 91
... 00’00AC 2B / 00’0084 21 / 00’00F4 3D / 00’00B0 2C / 00’00B4 2D / 00’00B8 2E / 00’00BC 2FH/ 00’0118 46 / 00’0114 45 / 00’0110 44 / Micronas ...
Page 92
... H Version 2.1 Interrupt Trap Vector Number Location 00’00F0 3C / 00’00EC 3B / 00’00E8 3A / 00’00E4 39 / 00’0080 20 / 00’010C 43 / 00’004C 4C / Reset conditions have H and 00’01FC . H H Micronas ...
Page 93
... Trap Trap Number Priority III – [0B – – Any Current – [00 – CPU Priority H Micronas ...
Page 94
... IE bit of this register. Arbitration between sources connected to the same node must be performed by the interrupt handler associated with this node. For low rate requests, the software overhead is not critical PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 95
... Again the group priority increases with the numerical value of GLVL the lowest and Interrupt and Trap Functions xxIR xxIE - - - the highest priority level the highest group priority. B PRELIMINARY DATA SHEET Version 2.1 Reset Value ILVL GLVL rw rw Micronas ...
Page 96
... Note: All sources that request PEC service must be programmed to different PEC channels. Otherwise an incorrect PEC channel may be activated PRELIMINARY DATA SHEET Interrupt and Trap Functions will terminate the Idle mode and B ) selects the PEC channel group B ILVL PEC Channel # Version 2.1 ) will B ) selects the PEC B GLVL UED11127 Micronas ...
Page 97
... PRELIMINARY DATA SHEET Interrupt and Trap Functions Type of Service COUNT PEC service, channel 7 PEC service, channel 6 PEC service, channel 2 CPU interrupt, level 13, group priority 2 CPU interrupt, level 1, group priority 3 CPU interrupt, level 1, group priority 0 No service! Version 2.1 H Micronas ...
Page 98
... Interrupt Enable bit IEN globally enables or disables PEC operations and the acceptance of interrupts by the CPU. When IEN is cleared, no new interrupt requests are Interrupt and Trap Functions MUL - - - USR0 PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 Micronas ...
Page 99
... When IEN is set to ‘1’, all interrupt sources, which have been individually enabled by the interrupt enable bits in their associated control registers, are globally enabled. Note: Traps are non-maskable and are therefore not affected by the IEN bit PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 100
... Counts PEC transfers (bytes or words) and influences the channel’s action. BWT Byte / Word Transfer Selection 0: Transfer a Word. 1: Transfer a Byte Interrupt and Trap Functions INC(1..0) BWT rw rw PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 COUNT (7...0) rw Micronas ...
Page 101
... PEC channel action depends on the previous content of COUNT Interrupt and Trap Functions Reg. Space Register Address SFR PECC4 FEC8 SFR PECC5 FECA SFR PECC6 FECC SFR PECC7 FECE PRELIMINARY DATA SHEET Version 2.1 Reg. Space / 64 SFR SFR SFR SFR H H Micronas ...
Page 102
... Move a Byte / Word Leave request flag set, which triggers another request No action! Activate interrupt service routine rather than PEC channel. ) activates the interrupt H in bit field COUNT. In this case after a transfer the request flag is not H H Version 2.1 , and the CPU is H Micronas ...
Page 103
... These flags indicate a channel PRELIMINARY DATA SHEET Interrupt and Trap Functions Linked PEC Channel PEC Channel B channel 1 channel 3 channel 5 channel 7 Version 2.1 channel 0 channel 2 channel 4 channel 6 Micronas ...
Page 104
... RAM of the M2 just below the bit-addressable area (see Figure 5-2 Interrupt and Trap Functions PRELIMINARY DATA SHEET Version 2 linked PEC H H Reset Value: 0000 Micronas ...
Page 105
... H 00’FCF4 SRCP1 H 00’FCF2 DSTP0 H 00’FCF0 SRCP0 PRELIMINARY DATA SHEET Version 2.1 00’FCEE H 00’FCEC H 00’FCEA H 00’FCE8 H 00’FCE6 H 00’FCE4 H 00’FCE2 H 00’FCE0 H UED11128 Reset Value: 0000 PECSSN (7...0) rw Micronas ...
Page 106
... M2 supports this function with two features Interrupt and Trap Functions Reg. Space Register Address SFR PECSN4 FED8 SFR PECSN5 FEDA SFR PECSN6 FEDC SFR PECSN7 FEDE PRELIMINARY DATA SHEET Version 2.1 Reg. Space / 6C SFR SFR SFR SFR H H Micronas ...
Page 107
... Interrupt and Trap Functions Interpretation 0 PEC service channels X Interrupt Class 1 5 sources on 2 levels X Interrupt Class 2 9 sources on 3 levels X X Interrupt Class 3 5 sources on 2 levels No service! PRELIMINARY DATA SHEET Version 2.1 Micronas ...
Page 108
... The data page pointers and the context pointer are not affected PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 109
... EXECUTE WRITEBACK 1 IR-Flag 0 Figure 5-4 Pipeline Diagram for Interrupt Response Time Interrupt and Trap Functions Cycle 2 Cycle TRAP ( Interrupt Response Time PRELIMINARY DATA SHEET Version 2.1 Cycle 4 I1 TRAP (2) TRAP N UED11129 Micronas ...
Page 110
... Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: • The worst case interrupt response time, including external accesses, will occur when instructions N, N+1 and N+2 are executed out of external memory, instructions N PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 111
... The PEC response time defines the time between an interrupt request flag of an enabled interrupt source being set and the PEC data transfer being started. The basic PEC response time for the instruction cycles PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 112
... Interrupt and Trap Functions Cycle 1 Cycle 2 Cycle PEC PEC Response Time PRELIMINARY DATA SHEET Version 2.1 Cycle PEC N UED11130 Micronas ...
Page 113
... The interrupt inputs are sampled every 8 states (16 TCL), i.e. external events are scanned and detected in timeframes of 16 TCL. M2 provides 8 interrupt inputs that are sampled every 2 TCL, so external events are captured faster than with standard interrupt inputs PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 114
... In Sleep mode, no clock is available for sampling, but interrupt request detection is still possible on fast interrupt request lines using asynchronous logic Interrupt and Trap Functions EXI4ES EXI3ES EXI2ES rw rw PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 EXI1ES EXI0ES Micronas ...
Page 115
... Table 5-1). PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and the CPU level in the PSW register is set to the highest possible priority level (i.e. level PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions through 00’01FC will be branched Micronas ...
Page 116
... Protection Fault Flag A protected instruction with an illegal format has been detected Interrupt and Trap Functions UND - - - - - OPC - - - PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 PRT ILL ILL ILL - FLT OPA INA BUS - Micronas ...
Page 117
... In the case where e.g. an Undefined Opcode trap (class B) occurs simultaneously with an NMI trap (class A), both the NMI and the UNDOPC flag is set, the IP of the instruction with the undefined opcode is pushed onto the system stack, but the NMI trap is executed PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 118
... SP. When an implicit increment of the SP is made through a POP or return instruction, the IP value pushed is the address of the following instruction. When the SP is incremented PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 119
... ILLBUS flag in the TFR register is set, and the CPU enters the illegal bus access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 120
... This function is very advantageous in Slow Down or in Sleep mode if, for example, the A/D converter input shall be used to wakeup the system. The register EXISEL is used to switch alternate interrupt sources to the interrupt controller. The EXISEL register is defined as follows PRELIMINARY DATA SHEET Version 2.1 Interrupt and Trap Functions Micronas ...
Page 121
... Input from default pin ANDed with “alternate source” Fast Alternate Source (input FEIxIN_B) Interrupt 0 ADWINT 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved PRELIMINARY DATA SHEET Interrupt and Trap Functions EXI4SS EXI3SS EXI2SS Version 2.1 Reset Value: 0000 EXI1SS EXI0SS rw rw Micronas ...
Page 122
System Control & Configuration ...
Page 123
... Power Management modes (Idle, Sleep, Power Down) • Watchdog timer • Identification registers for Core (CPU, SCU, OCDS) and system (manufacturer, chip version, memory) identification These functions are explained in further details in the following paragraphs PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Micronas ...
Page 124
... A complete power-on reset requires an active RSTIN time until a stable clock signal is available. The on-chip oscillator needs about stabilize PRELIMINARY DATA SHEET System Control & Configuration Short-cut Condition PONR Power-on SHWR 16 TCL < t LHWR > 2048 TCL RSTIN WDTR WDT overflow SWR SRST command Version 2.1 2048 TCL t RSTIN Micronas ...
Page 125
... Reset Values for the Controller Core Registers During the reset sequence the registers of the C166 CBC are preset with a default value. Most C166 CBC SFRs are cleared to zero, so the interrupt system is off after reset PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Micronas ...
Page 126
... R0) and the PEC source and destination pointers (SRCP7 … SRCP0, DSTP7 … DSTP0), which are mapped into the internal RAM, are also unchanged after a warm reset, software reset or watchdog reset, but are undefined after a power-on reset PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Micronas ...
Page 127
... RAM of the M2 via the System Control & Configuration PRELIMINARY DATA SHEET Version 2.1 on PORT4 will select the H Reset Value: 00XX SALSEL(2.. ENA r Micronas ...
Page 128
... Note: The selected number of segment address lines cannot be changed via software after reset PRELIMINARY DATA SHEET System Control & Configuration , the bootstrap loader is off. H Directly Accessible Address Space 4 MByte (Default without pull-downs) 2 MByte 1 MByte 512 KByte 256 KByte 128 KByte 128 KByte 128 KByte Version 2.1 Micronas ...
Page 129
... The commands of the (unlock) command sequence are characterized by certain pattern words (such as AAAA an 8-bit password. For command definition see the following state diagram (Figure 6-1 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration ) or by patterns combined with H Micronas ...
Page 130
... H registers for one write access if current security level is in low protected mode.) PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 Micronas ...
Page 131
... Reserved ‘110’: Reserved ‘111’: Reserved The following registers are defined as protected (security) registers: • SYSCON1 • SYSCON2 • SYSCON3 System Control & Configuration PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 PASSWORD r Micronas ...
Page 132
... It is recommended to use an atomic sequence for all command sequences PRELIMINARY DATA SHEET System Control & Configuration 1) Command 3 or any other SCU Register Write Access State 0 Command 2 or any other SCU Register Write Access Command 1 or any other SCU Register Write Access Command 1 State 1 Version 2.1 State 3 State 2 UED11131 Micronas ...
Page 133
... To return from Sleep mode, external, wake up- or RTC System Control & Configuration Idle Sleep MHz/ no clock/ stopped stopped MHz 3 MHz 3 MHz 3 MHz 3 MHz 3) off PRELIMINARY DATA SHEET Version 2.1 Power Down on off off off no clock/ stopped 2) off off off off off off Micronas ...
Page 134
... CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction PRELIMINARY DATA SHEET System Control & Configuration Sleep external, wake up- or RTC- IRQ Version 2.1 Power Down HW-reset Micronas ...
Page 135
... Before entering into one of the power save modes the external SDRAM must be put into self-refresh-mode by use of register EBIDIR (see Chapter 4.5 PRELIMINARY DATA SHEET System Control & Configuration Denied CPU Interrupt Request Accepted IDLE Instruction Idle Mode Denied PEC Request Executed PEC Request Version 2.1 UED11132 V pins. DD Micronas ...
Page 136
... Power Down Mode Note: This register is a protected register; it’s security level is automatically set to full write protection after execution of the EINIT instruction System Control & Configuration PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0001 SLEEPCON rw Micronas ...
Page 137
... Byte Mask Signals for SDRAM Oscillator Input/Output Reset Input Pin Chip Select Signals Clock Signals for SDRAM CVBS Input Signals Analog RGB Output Contrast Reduction and Blanking Pin Sync Inputs/Outputs for the Display CSROM CS3 are for general control of external , , Version 2.1 Micronas ...
Page 138
... COR can be generated separately as well, in which case no RSTOUT is available. HSYNC and VSYNC are bidirectional pins which are used to synchronize external video source or to deliver a stable horizontal and vertical sync timing to external components PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Micronas ...
Page 139
... XADRS3 - XADRS6 (not used) ADDRSEL1 - ADDRSEL4 (not used) XBCON1 XBCON2 XBCON3 - XBCON6 (not used) BUSCON0 BUSCON1 - BUSCON4 (not used) XPERCON PRELIMINARY DATA SHEET System Control & Configuration Value E444 H 0E03 H 0E83 H 0000 H 0000 H 05BF H 05BF H 0000 H 15B7 H 0000 H 0003 H Version 2.1 Micronas ...
Page 140
... In this case the Watchdog Timer Reset Indication Flag (WDTR) in register WDTCON will be set PRELIMINARY DATA SHEET System Control & Configuration WDT Control Clear MUX WDT Low Byte WDTIN f /128 by setting bit WDTIN. The CPU Version 2.1 WDTREL WDT High Byte WDTR UEB11133 with the frequency H Micronas ...
Page 141
... Here is the description of the Watchdog timer SFRs System Control & Configuration – <WDTREL> ⌠ ))/ CPU Prescaler for 2 (WDTIN = ‘0’) 33.33 MHz 3 MHz 25 32 3.3 ms 4.13 ms 6.55 ms 8.19 ms PRELIMINARY DATA SHEET Version 2.1 [1] f CPU 128 (WDTIN = ‘1’) 33.33 MHz 3 MHz 1.64 ms 2.05 ms 211 ms 264 ms 419 ms 524 ms Micronas ...
Page 142
... System Control & Configuration CPU f /128 CPU WDT( PRELIMINARY DATA SHEET Version 2.1 Reset Value: 00XX LHW SHW SW WDT WDT Reset Value: 0000 Micronas ...
Page 143
... Therefore a long hardware reset (LHWR) will be recognized in any case PRELIMINARY DATA SHEET System Control & Configuration after any possible reset event, H Reset Indication Flags LHWR SHWR SWR Version 2.1 WDTR – – – X Micronas ...
Page 144
... Context Pointer CP: FA00 Register STKUN: FA40 Stack Pointer SP: FA40 Register STKOV: FA0C Register S0CON: 8001 System Control & Configuration Int. Boot ROM BSL-routine MHz CPU <-> PRELIMINARY DATA SHEET Version 2.1 32 bytes User Software UET11134 Micronas ...
Page 145
... Accesses to the external ROM area are partly redirected, while the BSL mode. All code fetches to segment 0 are made from the special Boot-ROM, while data accesses read from the external user ROM PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Micronas ...
Page 146
... IDSCU, for CSCU identification, • DIPX version bit field, for OCDS identification. 6.9.1 System Identification These identific ID register description IDMANUF MANUF System Control & Configuration PRELIMINARY DATA SHEET Version 2.1 Reset Value: XXXX DEPT r Micronas ...
Page 147
... SDA 6000 Bit Function MANUF Manufacturer This is the JEDEC normalized manufacturer code. 0C1 :Infineon Technologies H 020 : SGS-Thomson H DEPT Department Indicates the department within Micronas and Infineon Technologies CAD Macrocells IDCHIP CHIPID r Bit Function Revision Device Revision Code Identifies the device step where the first release is marked ‘ ...
Page 148
... V Voltage ⌠ <PROGVDD>/256 [ Voltage ⌠ <PROGVPP>/256 [ ’ in both bit fields PRELIMINARY DATA SHEET Version 2.1 Reset Value: XXXX PROGVDD r Reset Value: XXXX RIX - - r Micronas ...
Page 149
... For Rev. 2.0 derivatives, the current value is 0000 System Control & Configuration CBC Rev SCU Revision Number . H PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0061 Core Reset Value: 0000 Micronas ...
Page 150
... Port 8-bit bidirectional I/O port which can also serve as fast external interrupt input (sample rate PRELIMINARY DATA SHEET System Control & Configuration Open Drain Control Registers DP2 DP3 ODP3 DP6 ODP6 Version 2.1 2 C-bus, Special Control Registers P5BEN ALTSELOP6 UEA11135 Micronas ...
Page 151
... DP2 Port line P2 input (high-impedance). DP2 Port line P2 output System Control & Configuration P2.9 P2 DP2. DP2 PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 Reset Value: 0000 Micronas ...
Page 152
... Reset Value: 0000 P3.4 P3.3 P3.2 P3.1 P3 Reset Value: 0000 DP3. DP3. DP3. DP3. DP3 Reset Value: 0000 ODP3. ODP3. ODP3. ODP3. ODP3 Micronas ...
Page 153
... During reset, the user specific portion of the system start-up configuration is input via Port 4. The complete configuration (user specific as well as hardwired settings) can be read at runtime from register RP0H. For a detailed description refer to Chapter 6. PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Micronas ...
Page 154
... System Control & Configuration P4L.5 P4L.4 P4L.3 P4L.2 P4L.1 P4L P4.5 rw PRELIMINARY DATA SHEET Version 2.1 Reset Value: XXXX Reset Value: 0000 P4.4 P4.3 P4.2 P4.1 P4 Micronas ...
Page 155
... Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Altern. Function CSENA = 1 Gen. Purp. I PRELIMINARY DATA SHEET Version 2.1 Altern. SALSEL = 010 or Function 001 or 000 SALSEL = 011 A16 Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Reset Value: 0000 P5.3 P5.2 P5.1 P5 Micronas ...
Page 156
... Port data register P6 bit System Control & Configuration P6.6 P6 PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 P5B - P5B P5B P5B EN.3 EN.2 EN.1 EN Reset Value: 0000 P6.4 P6.3 P6.2 P6.1 P6 Micronas ...
Page 157
... C Bus Clock Line Bus Data Line 1 no alternate function Bus Data Line 2 PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 Reset Value: 0000 ODP6. ODP6. ODP6. ODP6. ODP6 Micronas ...
Page 158
... SELP6 General Purpose Port Functionality enabled for Line P6.y. SELP6 Alternate Function enabled for Line P6. System Control & Configuration SEL SEL P6.6 P6 PRELIMINARY DATA SHEET Version 2.1 Reset Value: 0000 SEL SEL SEL SEL SEL P6.4 P6.3 P6.2 P6.1 P6 Micronas ...
Page 159
... SDA 6000 PRELIMINARY DATA SHEET Version 2.1 System Control & Configuration Micronas ...
Page 160
Peripherals ...
Page 161
... SDA 6000 7 Peripherals All of the peripherals described in the following paragraphs are clocked with the same f clock as the CPU ( ). Depending on the mode (normal or Idle), this frequency is hw_clk 33.33 MHz or 3 MHz PRELIMINARY DATA SHEET Version 2.1 Peripherals Micronas ...
Page 162
... An overflow/underflow of core timer T3 is indicated by the output toggle latch T3OTL whose state may be output on related line T3OUT. The auxiliary timers T2 and T4 may additionally be concatenated with the core timer, or used PRELIMINARY DATA SHEET Version 2.1 Peripherals f /4. The auxiliary hw_clk f /2. An additional hw_clk Micronas ...
Page 163
... Setting bit T3R will start the timer, clearing T3R stops the timer PRELIMINARY DATA SHEET U/D GPT1 Timer T2 T2 Mode Control Reload Capture T3 Mode GPT1 Timer T3 Control U/D Capture Reload T4 Mode Control GPT1 Timer T4 U/D Version 2.1 Peripherals Interrupt Request Interrupt Request Interrupt Request UEB11195 Micronas ...
Page 164
... T3OUT. If this line is linked to an external port pin, which has to be configured as output, T3OTL can be used to control external HW Bit T3UD Count Direction 0 Count Up 1 Count Down 0 Count Up 0 Count Down 1 Count Down 1 Count Up PRELIMINARY DATA SHEET Version 2.1 Peripherals Micronas ...
Page 165
... PRELIMINARY DATA SHEET Version 2.1 Peripherals divided by a programmable f for timer T3 BPS1 ⌠ 2 <T3I> f [MHz] hw_clk 101 110 111 256 512 1024 130.20 65.10 32.55 kHz kHz kHz 7.68 15.36 30.72 ← s ← s ← s 503 1 2. Micronas ...
Page 166
... Figure 7-3 Block Diagram of Core Timer T3 in Gated Timer Mode Core Timer Tx Up/ Down TxR 0 MUX 1 TxUDE Core Timer Tx Up/ Down TxR 0 MUX 1 TxUDE PRELIMINARY DATA SHEET Version 2.1 Peripherals Interrupt Request UEB11196 TxOTL TxOUT TxOE Interrupt Request UEB11197 Micronas ...
Page 167
... Negative transition (falling edge) on T3IN Any transition (rising or falling edge) on T3IN Reserved. Do not use this combination PRELIMINARY DATA SHEET ’, line T3IN must have a high level in order to enable B Core Timer Tx TxOTL Up/ Down Version 2.1 Peripherals TxOFL TxOUT TxOE Interrupt Request UEB11198 Micronas ...
Page 168
... RDIR Change Detection 0 MUX XOR 1 T3UDE ’ or edge detection ‘111 B PRELIMINARY DATA SHEET Version 2.1 Peripherals f /8 (BPS1 = ‘01’). hw_clk f cycles (BPS1 = ‘01’) hw_clk T3OTL T3OUT T3OE Interrupt Request Edge Interrupt T3M T3 Rotation CHDIR Interrupt T3M UEB11199 ’ Micronas ...
Page 169
... Pins associated with lines T3IN and T3EUD must be configured as input. • The T3UDE bit must be set to enable automatic direction control Input - Input - T0 + Interrupt - Signal Conditioning ’ or ‘111 ’ PRELIMINARY DATA SHEET Version 2.1 Peripherals Microcontroller UED11136 Micronas ...
Page 170
... T3I = ’011 Figure 7-7 Evaluation of the Incremental Encoder Signals cycles (BPS = 01) before it changes. hw_clk T3IN Input Falling Rising Up Up Down Down Jitter Backward Jitter Down ’. B PRELIMINARY DATA SHEET Version 2.1 Peripherals f / hw_clk T3EUD Input Falling Down Up Forward Up UET11137 Micronas ...
Page 171
... Run control for auxiliary timers T2 and T4 can be handled by the associated Run Control Bit T2R, T4R in register T2CON/T4CON. Alternatively, a remote control option (T2RC, T4RC set) may be enabled to start and stop T2/T4 via the run bit T3R of core timer T3 PRELIMINARY DATA SHEET Jitter Backward Jitter Down ’. B Version 2.1 Peripherals Forward Up UET11138 Micronas ...
Page 172
... T3OTL. Bit field TxI in the respective control register TxCON selects the triggering transition (see Table 7-6 PRELIMINARY DATA SHEET Auxiliary Timer Tx Up/ Down TxR 0 MUX 1 TxUDE Version 2.1 Peripherals Interrupt Request UEB11200 Micronas ...
Page 173
... The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. In this case T3 can operate in timer, gated timer or counter mode PRELIMINARY DATA SHEET Version 2.1 Peripherals f /8 (BPS1 hw_clk f cycles (BPS1 = ‘01’) hw_clk Micronas ...
Page 174
... Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R PRELIMINARY DATA SHEET Core Timer Ty TyOTL Up/Down Auxiliary Timer Tx TxIR ’. In reload mode the core timer T3 is reloaded with B Version 2.1 Peripherals TyOUT TyOE Interrupt Request Interrupt Request UES11201 Micronas ...
Page 175
... T3OTL, the other is programmed for a reload on a negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers Core Timer T3 Up/Down T3OTL PRELIMINARY DATA SHEET Version 2.1 Peripherals Interrupt Request Interrupt Request T3OUT T3OE UES11202 Micronas ...
Page 176
... In this case both reload registers would try to load the core timer at the same time. If this combination is selected disregarded and the contents of T4 reloaded Reload Register T2 Core Timer T3 T3OTL Reload Register T4 PRELIMINARY DATA SHEET Version 2.1 Peripherals Interrupt Request T3OUT T3OE Interrupt Request Interrupt Request UES11203 Micronas ...
Page 177
... In capture mode the contents of the core timer are B Core Timer T3 Up/Down T3OTL PRELIMINARY DATA SHEET Version 2.1 Peripherals Interrupt Request Interrupt Request T3OUT T3OE UES11204 f hw_clk Micronas ...
Page 178
... Control CAPIN MUX T3IN/ T3EUD CT3 n f Mode hw_clk Control Figure 7-14 Structure of Timer Block U/D GPT2 Timer T5 Clear Capture GPT2 CAPREL Clear GPT2 Timer T6 U/D T6 PRELIMINARY DATA SHEET Version 2.1 Peripherals Interrupt Request Interrupt Request Interrupt Request T6OTL UES11205 Micronas ...
Page 179
... T6I. The input frequency r resolution are scaled linearly with lower clock frequencies T6 the following formula: f hw_clk BPS2 ⌠ BPS2 ⌠ [ms <T6I> PRELIMINARY DATA SHEET Version 2.1 Peripherals f for timer T6 and its can be seen from hw_clk <T6I> f [MHz] hw_clk Micronas ...
Page 180
... T6. The descriptions, figures and tables apply accordingly with one exception: • Overflow/Underflow monitoring is not supported (no output toggle latch PRELIMINARY DATA SHEET Core Timer T6 Up/ Down T6R T6UD Version 2.1 Peripherals T6OFL Interrupt Request T6OTL UEB11206 Micronas ...
Page 181
... Either a positive, a negative, or both a positive and a negative transition at line CAPIN can be selected to trigger the capture function, or transitions on input T3IN or input PRELIMINARY DATA SHEET Core Timer Ty TyOTL Up/Down Auxiliary Timer Tx TxIR Up/Down Version 2.1 Peripherals Interrupt Request TyOFL Interrupt Request UES11207 Micronas ...
Page 182
... T3EUD CT3 CI Figure 7-17 Timer Block 2 Register CAPREL in Capture Mode PRELIMINARY DATA SHEET f cycles (BPS2 = ‘01’) before it hw_clk . This option is controlled by H Up/Down Auxiliary Timer T5 T5CLR T5CC T5SC CAPREL Register Version 2.1 Peripherals f /2 hw_clk Interrupt Request Interrupt Request UEB11208 Micronas ...
Page 183
... T5SC and T6SR, by setting both bits the two functions can be enabled simultaneously. This feature can be used to generate an output frequency that is a multiple of the input frequency PRELIMINARY DATA SHEET to 0000 (when counting up) or when it underflows H H T6SR Version 2.1 Peripherals Interrupt Request T6OFL UEB11209 Micronas ...
Page 184
... Upon each underflow, the interrupt request flag T6IR will be set and PRELIMINARY DATA SHEET Up/Down Auxiliary Timer T5 T5CLR T5CC T5SC CAPREL Register T6CLR T6SR Core Timer T6 Up/Down f /4, uses the value in register CAPREL hw_clk Version 2.1 Peripherals Interrupt Request Interrupt Request Interrupt Request T6OFL UEB11210 Micronas ...
Page 185
... Description Timer 2 Control Register Timer 3 Control Register Timer 4 Control Register Timer 5 Control Register Timer 6 Control Register Capture/Reload Register Timer 2 Register Timer 3 Register Timer 4 Register Timer 5 Register Timer 6 Register PRELIMINARY DATA SHEET Version 2.1 Peripherals /100 for /99 and the H D Micronas ...
Page 186
... Timer/Counter 3 runs Timer 3 Up/Down Control (when T3UDE = ‘0’) 0 Counting ‘Up’ 1 Counting ‘Down’ Timer 3 External Up/Down Enable 0 Counting direction is internally controlled Counting direction is externally controlled by line T3EUD PRELIMINARY DATA SHEET Version 2.1 Peripherals T3M T3I rw rw Micronas ...
Page 187
... The bit is set on a change of the count direction of timer 3. The bit has to be reset by SW change in count direction was detected 1 A change in count direction was detected Timer 3 Rotation Direction 0 Timer 3 counts up 1 Timer 3 counts down Version 2.1 Peripherals /8 /4 /32 /16 Micronas ...
Page 188
... Reserved. Do not use this combination Prescaler for Prescaler for f f hw_clk hw_clk (BPS1 = 01) (BPS1 = 10 128 32 256 64 512 128 1024 256 2048 512 4096 PRELIMINARY DATA SHEET Version 2.1 Peripherals Prescaler for f hw_clk (BPS1 = 11 128 256 512 1024 2048 Micronas ...
Page 189
... Timer/Counter x runs Timer x Up/Down Control (when TxUDE = ‘0’) 0 Counting ‘Up’ 1 Counting ‘Down’ Timer x External Up/Down Enable 0 Counting direction is internally controlled Counting direction is externally controlled by line TxEUD PRELIMINARY DATA SHEET Version 2.1 Peripherals TxM TxI rw rw Micronas ...
Page 190
... Timer x Count Direction Change The bit is set on a change of the count direction of timer x. The bit has to be reset by SW change in count direction was detected 1 A change in count direction was detected Timer x Rotation Direction 0 Timer x counts up 1 Timer x counts down Version 2.1 Peripherals Micronas ...
Page 191
... Reserved. Do not use this combination Prescaler for Prescaler for f f hw_clk hw_clk (BPS1 = 01) (BPS1 = 10 128 32 256 64 512 128 1024 256 2048 512 4096 PRELIMINARY DATA SHEET Version 2.1 Peripherals Prescaler for f hw_clk (BPS1 = 11 128 256 512 1024 2048 Micronas ...
Page 192
... Timer 6 is not cleared on a capture event 1 Timer 6 is cleared on a capture event Timer 6 Reload Mode Enable 0 Reload from register CAPREL disabled 1 Reload from register CAPREL enabled PRELIMINARY DATA SHEET Version 2.1 Peripherals T6M T6I hw_clk f /2 hw_clk f /16 hw_clk f /8 hw_clk Micronas ...
Page 193
... Reserved. Do not use this combination! 011 Reserved. Do not use this combination! 1XX Reserved. Do not use this combination PRELIMINARY DATA SHEET Prescaler for f (BPS2 = 01) (BPS2 = 10) hw_clk 128 256 512 1024 2048 Version 2.1 Peripherals Prescaler for f (BPS2 = 11) hw_clk 128 256 512 1024 Micronas ...
Page 194
... Timer 3 Capture Trigger Enable 0 Capture trigger from input line CAPIN 1 Capture trigger from T3 input lines Timer 5 Capture Correction just captured without any correction decremented by 1 before being captured PRELIMINARY DATA SHEET Version 2.1 Peripherals T5M T5I rw rw Micronas ...
Page 195
... Timer 5 is cleared on a capture operation Timer 5 Capture Mode Enable 0 Capture into register CAPREL disabled 1 Capture into register CAPREL enabled Prescaler for f (BPS2 = 01) (BPS2 = 10) hw_clk 128 256 512 1024 2048 Version 2.1 Peripherals Prescaler for f (BPS2 = 11) hw_clk 128 256 512 1024 Micronas ...
Page 196
... Interrupt is requested on overflow of timer 4 if counting up. Interrupt is requested on underflow of timer 4 if counting down. Interrupt is requested on overflow of timer 5 if counting up. Interrupt is requested on underflow of timer 5 if counting down. Interrupt is requested on overflow of timer 6 if counting up. Interrupt is requested on underflow of timer 6 if counting down. Version 2.1 Peripherals Micronas ...
Page 197
... Capture Mode (T2I = 101). Interrupt is requested on a trigger signal for a capture action to capture timer 3 in timer 4 Capture Mode (T4I = 101). Interrupt is requested on a trigger signal for a capture action of timer 5 to register CAPREL in Capture Mode (T5SC = 1). Version 2.1 Peripherals Micronas ...
Page 198
... Figure 7-21 shows the RTC block diagram Counter Registers T14REL T14 RTCRELH RTCH RTCRELL RTCL RTCH RTC Timer Count Register, High Word RTCL RTC Timer Count Register, Low Word RTCISNC RTC Interrupt Sub Node Control Register PRELIMINARY DATA SHEET Version 2.1 Peripherals Interrupt Control RTCISNC UEA11139 Micronas ...
Page 199
... M2. With typical values of T14REL = F448 RTC_T14INT Interrupt Subnode RTC0INT RTC1INT RTCRELL0 RTCRELL1 10 Bit 6 Bit 10 Bit 6 Bit RTCL0 RTCL1 PRELIMINARY DATA SHEET Version 2.1 Peripherals RTC_INT RTC2INT RTC3INT RTCREL2 RTCREL3 6 Bit 10 Bit 6 Bit 10 Bit RTCH2 RTCH3 UEB11140 , RTCRELL = 1018 and H H Micronas ...
Page 200
... Increment T14 Timer Value Setting this bit to 1 effects an increment of the T14 timer value. The bit is cleared by hardware after incrementation PRELIMINARY DATA SHEET Version 2.1 Peripherals Reset Value: 0003 T14 T14 0 RTC INC DEC Micronas ...