CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 187

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
28. DIGITbus System Description
28.1. Bus Signal and Protocol
The DIGITbus is a single line serial master-slave-bus that
allows clock recovery from the sign stream. Data on the bus
are represented by a pulse width modulated signal. There
are three different signs:
“0”: 25% High Time
“1”: 50% High Time
“T”: 75% High Time
A permanent high bus (100% High Time) means the bus is
passive high. The bus is active if there are consecutive T-
Signs, ones or zeros.
A permanent low bus (0% High Time) is interpreted as bus
reset or failure indicator. Reasons may be shorts or opens or
even a low level forced by a bus node to indicate an internal
failure or reset condition.
The sign “T” is used to provide a system wide clock for the
bus nodes and to separate the address and data fields and
consecutive telegrams.
A telegram normally consists of an address and a data field
separated by one “T”. These fields may be as long as neces-
sary. Thus the length of an address or data field may carry
information. The end is marked by a “T”. The end of a tele-
gram is marked by two T-Signs.
One system implementation may be confined to certain
address and/or data field lengths, thus reducing the hard-
ware or software requirements.
The transmitter of an address has to guarantee that the
address is preceded by four T-Signs at least.
An isolated data field is not possible. Each non “T” sequence,
which is preceded by two or more consecutive T-Signs must
be interpreted as an address. An address field is valid after
28.2. Other Features
There are two possibilities for a slave to signal a local event
to the master. They are called wake-up and bus reset.
28.2.1. Wake-up
If the DIGITbus is passive high (permanent high level for
more than one bit period) a slave may pull the bus line to low
Micronas
T
T
Address
0
bit time
1
T
Data
T
T
T
June 12, 2003; 6251-579-1PD
T
the reception of the following “T”. The minimum address
length is one bit. The minimum data field length is zero bit.
Telegrams with more than one data field are allowed too. For
instance TTTTAAATDDDDTDDDDDTT is a valid telegram
format on the DIGITbus.
A telegram consisting of an address only is possible too. The
length of the data field is zero in this case.
A data field is preceded by an address field and separated
from this by a single “T”. It is followed by one T-Sign. After
reception of two T-Signs the telegram is finished and valid.
In the idle phase (no information exchange) of the bus traffic,
only the bus clock is transmitted.
After the reception of two consecutive T-Signs all bus nodes
have to be prepared to receive a new telegram starting with
an address field. They are ready to send an address after the
reception of four consecutive T-Signs.
The modification of a T-Sign to a zero or one is done by pull-
ing the bus line to low (dominant state) at the right time. This
is done by a master sending an address or a data bit or by a
slave sending a data bit.
In case of reading data from a slave, the master first sends
the address. After receiving the address the slave waits one
T-Sign and then modifies the following T-Signs to zeros and
ones which the master can recognize.
Slaves do not have the possibility to become active on the
bus if they want to communicate a local event or if they need
data from a master. It is a polling bus. Only a master is able
to send an address. The master has to scan the slaves for
their data. But it is possible to transfer data from one slave
directly to another slave. The master has to transmit an
address for which one slave is the source and the second
slave is the destination. Telegrams on the bus are broad-
casted. Each bus node may receive them.
level. This will awake the master who has to store this event
in a flag, to start the bus clock and to scan the bus for the
source of this event. The minimum low time of the reset pulse
is 1/16 of the nominal bit time (1/Baudrate).
T
T
T
T
T
Address
T
T
T
T
CDC 32xxG-C
T
T
T
T
T
T
T
T
T
T
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