CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 90

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
If the ICU’s output is enabled by the Global Enable flag (GE)
the nIRQ input of the CPU is activated and held active until
acknowledged. The IRQ is granted by the CPU as soon as
the CPU internal IRQ flag (flag I in CPU register CPSR) is
enabled by SW. In the meantime between interrupt activation
in the ICU and granting by the CPU, higher priority interrupt
requests may be signaled to the ICU, raising the priority out-
put of the Priority Encoder.
The SW has to read the address where the Vector Table
Base register points to ([VTB]) in order to get the start
address of the ISR for the ISN with the currently highest
active priority (Fig. 11–3). A data fetch from this location gen-
erates an internal interrupt acknowledge signal (IAck). With
IAck the Active Priority Level Logic accepts the new priority
and internally saves the priority of the interrupted task. IAck
clears the P flag in the corresponding ISN and deactivates
the nIRQ output. The outputs of the Priority Encoder (regis-
ters PEPRIO and PESRC) change immediately their values
and show source number and priority of the next pending
interrupt. The ICU is ready for new interrupts now.
Before leaving the interrupt service routine, the SW has to
write to the address where VTB points to plus 0x100
([VTB]+0x100). A write to this location generates an internal
interrupt exit signal (IExit). With IExit the Active Priority Level
Logic internally deletes the priority of the current task and
outputs the priority of the interrupted task where the immedi-
ately following return instruction jumps to.
Fig. 11–3:
Each ISN has a dedicated source number. A maximum of 64
ISNs can be connected to the Priority Encoder. The Priority
Encoder outputs source number 0 as long as all ISNs output
priority 0 or no ISN is active or the comparator output is inac-
tive. This is to guarantee a valid state of the Priority Encoder
and return a valid start address even if no interrupt source is
active. The corresponding vector is the first in the vector
table (default vector). For this reason ISN0 can’t be used for
connecting an interrupt source, because ISN0 is not the only
user of the corresponding interrupt vector. For example,
reading the address location pointed to by the Vector Table
Base register while nIRQ is inactive will return the ISR start
address of ISN0.
Additional to the ISNs whose inputs are connected to a HW
module, some ISNs are necessary whose inputs are not con-
nected or unused. Those interrupts can be activated by SW
solely (delayed interrupt).
88
0FC
00C
100
0F8
0F4
0F0
008
004
000
Interrupt Vector Table
ISN63 ISR
ISN62 ISR
ISN61 ISR
ISN60 ISR
ISN2 ISR
ISN2 ISR
ISN1 ISR
ISN0 ISR
32 Bit
Exit
interrupt exit address
interrupt entry address
source number
Vector Table Base
June 12, 2003; 6251-579-1PD
The output of the Active Priority Level Logic may be forced by
writing a higher priority to the Forced Priority register. This
allows temporary raising of the priority of the currently run-
ning task. Writing the maximum priority to the Forced Priority
register is another way to disable the ICU because no ISN
can generate an IRQ. Raising of the priority in this way does
not take effect as long as nIRQ is active.
The Global Enable (GE) signal at the output of the compara-
tor disables the ICU output. It is impossible to inactivate an
active nIRQ output by modifying an ISN, the GE flag or forc-
ing the priority. Only IAck resets the nIRQ output.
The size of the ICU can be scaled in steps of 8 ISNs. This IC
has 40 Interrupt Source Nodes implemented (ISN0 to
ISN39). Derived parts can contain 40, 32 (ISN0 to ISN31),
24 (ISN0 to ISN23) or less ISNs.
The Pending flags P in the ISNs are operating even when the
ICU is disabled (CRI.GE = 0). To be exact, only the ICU out-
put is disabled. This avoids further interrupts. Interrupted
ISRs will be finished and the Act. Prio. Level stack will be
handled properly if those ISRs generate IExit before return-
ing.
Fig. 11–4:
Figure 11–4 shows the reset structure. Registers can’t be
written until the IRQ flag in the standby register SR1 is set.
The pending flags P in the ISNs are not reset by the standby
register. It can be operated by HW even while SR1.IRQ is
zero. Reading and writing of the P flags is impossible unless
SR1.IRQ is set to one.
reset
SR1.IRQ
Reset Structure
R Q
CRI.GE
PRELIMINARY DATA SHEET
R Q
reset CRI, AFP, ISN
and internal logic
disable nIRQ
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