CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 117

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
16.2. Timer T1 to T4
Timer T1 to T4 are 8bit auto reload down counters. They
serve to deliver timing reference signals to the ICU or to out-
put frequency signals.
Table 16–3 describes implementation specific HW Option
addresses and enable flags of T1 to T4.
Fig. 16–3: Timer T1 to T4 Block Diagram
16.2.1. Principle of Operation
16.2.1.1. General
The timer’s 8bit down-counter is clocked by the input clock
and counts down to zero. One clock count after reaching
zero, it generates an output pulse, reloads with the content of
the TIMx reload register and restarts its travel.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
16.2.1.2. Operation
The clock input frequencies are settable by HW options (see
Table 16–3 on page 116). After reset, the 8bit timer is in
standby (inactive).
Prior to entering active mode, proper SW initialization of the
U-Ports assigned to function as Tx-OUT outputs has to be
made (Table 16–3). The ports have to be configured Special
Out. Refer to “Ports” for details.
To initialize a timer, reload register TIMx can be set to the
desired time value already in standby mode.
For entering active mode, set the corresponding enable bit in
the standby registers (see Table 16–3 on page 116). The
timer will immediately start counting down from the time
value present in register TIMx.
During active mode, a new time value is loaded by simply
writing to register TIMx. Upon writing, the counter is reset,
and immediately starts counting down from the new time
value.
After reaching zero, on wrapping to 0xFF, the counter gener-
ates a reload signal, which can be used to trigger an inter-
rupt. The same signal is connected to a divide by two scaler
to generate the output signal Tx-OUT with a pulse duty factor
of 50%.
The interrupt source output of this module may be but must
not be connected to the interrupt controller. Please refer to
section Interrupt Controller.
Micronas
HW Option
enable
TxC
clk
&
w
clk
8 bit Auto-reload
Down counter
Reload-Reg.
8
June 12, 2003; 6251-579-1PD
t
clk
TIMx
underflow
Features
– 8bit auto reload counter
– Interrupt source output
– Frequency output
Returning Tx to standby mode by resetting its respective
enable bit will halt its counter and will set its outputs LOW.
The register TIMx remains unchanged.
The state of the down-counter is not readable.
16.2.1.3. Precautions
A load with a new value within a time period of < t
a scheduled Interrupt Source output signal, can no longer
cancel this signal. It will appear at the Interrupt Source out-
put anyway (See fig. 16–4 for details).
Furthermore, disabling the timer within a time period of < t
2 before a scheduled Interrupt Source output signal, will
immediately generate an extra Interrupt Source output sig-
nal. Reenabling the timer afterwards will lead to generation
of the previously scheduled Interrupt Source output signal,
because it was stored internally. This latter Interrupt Source
output signal will be generated even if a new time value is
loaded during the inactive time.
Thus after configuring and (re-)enabling the timer, or after
loading a new time value during active mode, wait at least
t
the interrupt channel.
clk
/2 before resetting the Pending Flag P and (re-) enabling
&
1/2 t
clk
CDC 32xxG-C
1/2
res
Tx
Interrupt
Source
Tx-OUT
clk
/2 before
115
clk
/