CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 54

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
5.3. Special Function ROM (SFR)
The job of the SFR is to enable the JTAG interface if neces-
sary. Further actions as there are download, Flash ROM pro-
gramming or debugging and monitoring have to be done via
JTAG interface.
If TEST2 pin is held high during reset, the Control Word from
the SFR is copied to the Control Register by HW. The SFR
Control Word is configured to start program execution from
the SFR, mirrored to location 0. The SFR Control Word dis-
ables JTAG.
5.3.1. Principle of operation
The first instruction of the SFR (Reset Vector) loads the
address of the next instruction in the original SFR
(0xF00100, above the SFR HW Options) into the program
counter. This causes a jump from the mirrored SFR to the
original SFR. The remaining part of the program is running in
the original SFR and remapping of the memory does not
influence correct operation of the SFR program.
If the TEST pin is detected low immediately after the SFR
Firmware was started, the security vector in the Flash ROM
is checked (Table 5–3). In case the security vector is set in
the application program, the application is started, otherwise
the JTAG interface is enabled and the program stays in an
endless loop to allow TAP access.
If the TEST pin is detected high immediately after the SFR
firmware was started, additional functions may be invoked,
selected by the digital levels at the analog input pins P0[1:0]
(Table 5–3).
This mode is not intended to be used within the applica-
tion environment but for test purposes only! It depends on
Table 5–3:
52
TEST
pin
0
0
1
1)
Inadvertent execution of critical code additionally blocked by HW decoding of TEST pin state.
SV
set
not set
x
Start up control by TEST pin and security vector (SV), TEST2 pin = 1
QFP 128
use application CW in flash to start the application
in flash
enable application JTAG to allow debugging
decode further input selection to
- run Test Program
- Erase Flash
- generate checksum
- indicate IDs
1)
June 12, 2003; 6251-579-1PD
the selected function if, what and how additional pins will be
used for further operations. For notifications UART0 is used
with 9600 Bd, 8 data bits, 2 stop bits, no parity and no kind of
handshake:
– P0[1:0] = 0: Erase Flash:
– P0[1:0] = 1: Run Test Program:
– P0[1:0] = 2: Check IDs:
– P0[1:0] = 3: Generate Checksum:
The watchdog is not triggered in the SFR program. Espe-
cially when the program is in the endless loop this would
cause problems. But this endless loop will not be reached in
ROM parts as long as the security vector is valid.
A blank check of the Flash ROM is executed to detect if it
is erased. If the Flash ROM is not clear, it is erased and
checked again, until detected as completely blank.
When finished, “Flash is blank” is indicated via UART 0.
For test purposes an endless program sequence is exe-
cuted, using most parts of the chip internal modules. Be
sure to run this program in the test environment only!
ROM and Factory ID are read out of the Flash ROM and
indicated via UART 0. In addition to the 16 bit ROM ID
(RID) the adjacent reserved 2 bytes are displayed as
upper half word of the RID, e.g.:
“RID: 0x0x56BC78AB
FID: 0xDE9ACDFE”
A 32-bit checksum of the whole Flash ROM content is
generated by summing up all data words, without consid-
ering carry-overs. The result is shown as hex value via
UART 0, e.g.: “CHECKSUM: 0x3456BCDE”.
EMU
use application CW in emulation memory to start
the application in emulation memory
PRELIMINARY DATA SHEET
Micronas