CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 174

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
as soon as a dominant bus level is detected, or the sleep flag
is deleted.
GRSC
r0:
r/w1:
The microprocessor can set this flag in order to initiate a
transmit telegram search at the beginning of the Com. Area.
The BI resets the bit. The BI also sets the GRSC flag if the
flag RSC has been set in a telegram descriptor of a Tx-Tg
just operated, and thereby initiates a rescan. If the micropro-
cessor writes a zero, nothing happens.
EIE
r/w0:
r/w1:
GRIE
r/w0:
r/w1:
GTIE
r/w0:
r/w1:
BOST
r/w0:
r/w1:
The flag HLT is set by the BI after leaving the Bus-Off recov-
ery sequence. The SW has to restart the CAN module in this
case after re-initialisation. Consider the flag HACK even in
this case.
HACK
r0:
r1:
Is set by the BI when it enters the halt mode. It is deleted
again when the halt mode is exited.
BOFF
r0:
r1:
With this flag the BI indicates whether the node is still
actively participating in the bus. If the transmit error counter
reaches a value of > 255 (overflow), the node is separated
from the bus and the flag is set. The Bus-Off mode is left
after the Bus-Off recovery sequence. The flag CANx-
CTR.BOST defines the behavior after leaving Bus-Off mode.
EPAS
r0:
r1:
With this flag the BI indicates whether the node is still partici-
pating in the bus with active Error Frames. If an error counter
has reached a value > 127, the node only transmits passive
error frames and the flag is set.
ERS
r0:
r1:
This flag is set when the BI detects an error and the apropri-
ate error flag is not masked in the error status mask register.
It is set even if an error counter is greater than 96. It means
that a bit has been set in the error status register. As soon as
172
CANxSTR
r
HACK
1
7
BOFF
0
6
Error-Interrupt-Enable
No Errors.
Global Rescan
Don’t rescan.
Rescan.
Disabled.
Enabled.
Global Rx-Interrupt-Enable
Disabled.
Enabled.
Global Tx-Interrupt-Enable
Disabled.
Enabled.
Bus-Off Stop Select
Don’t stop when leaving Bus-Off mode.
Stop when leaving Bus-Off mode.
Halt-Acknowledge
Running.
Halted.
Bus-Off
Bus active.
Bus off.
Error-Passive
Error active.
Error passive.
Error-Status
Errors.
EPAS
Status Register
0
5
ERS
0
4
rsvd
x
3
rsvd
2
x
rsvd
x
1
June 12, 2003; 6251-579-1PD
rsvd
0
x
Res
all the flags in the error status register are either deleted or
masked, ERS is also deleted.
As long as a bit is set in the CANxESTR and not masked, the
ERS bit is also set in the status register. If EIE has been set
in the control register, an interrupt is triggered too; i.e. the
value 254 is entered in the register CANxIDX as soon as it is
free, and the interrupt source output is triggered.
To erase a bit in the CANxESTR the user must write a one at
the appropriate place. Places at which he writes a zero will
not be changed. Because it makes sense to erase only those
bits which have previously been read, only the value which
has been read has to be re-written.
Read-Modify-Write operations on single flags of this register
must be avoided. Unwanted clearing of other flags of this
register may be the result otherwise.
GDM
r0:
r1:
w0:
w1:
Is set by the BI when it is aroused from the sleep mode by a
dominant bus level. The user must delete it.
CTOV
r0:
r1:
w0:
w1:
Is set by the BI when the capture timer (CTIM) overflows.
The user must delete it.
ECNT
r0:
r1:
w0:
w1:
Is set by the BI as soon as the transmit error counter or the
receive error counter exceeds a limit value. The user must
delete it.
BIT
r0:
r1:
w0:
w1:
Is set by the BI when a transmitted bit is not the same as the
bit received. The user must delete the flag.
STF
r0:
r1:
w0:
w1:
Is set by the BI when 6 identical bits are received succes-
sively in one Tg. The user must delete it.
CRC
r0:
r1:
w0:
r/w
CANxESTR
GDM
0
7
CTOV
0
6
Good Morning
No wake-up.
Wake-up.
Unaffected.
Clear.
Capture Time Overflow
No overflow.
Overflow.
Unaffected.
Clear.
Error Counter Level
No error counter.
Error counter.
Unaffected.
Clear.
Bit Error
No bit error.
Bit error.
Unaffected.
Clear.
Stuff Error
No stuff error.
Stuff error.
Unaffected.
Clear.
CRC Error
No stuff error.
Stuff error.
Unaffected.
ECNT
Error Status Register
0
5
BIT
0
4
PRELIMINARY DATA SHEET
STF
0
3
CRC
0
2
FRM
0
1
Micronas
ACK
0
0
Res