CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 60

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
PWM7
r/w1:
r/w0:
PWM5
r/w1:
r/w0:
PWM3
r/w1:
r/w0:
PWM1
r/w1:
r/w0:
6.4. UVDD Analog Section
6.4.1. VBG Generator
The low-power VBG Generator generates bias signals which
are necessary for the operation of all UVDD Analog Section
modules. Furthermore, it produces a reference voltage VBG,
that is delivered to the VDD and FVDD Regulators, the
6.4.2. VDD Regulator
The VDD Regulator generates the 2.5V VDD supply voltage
for the internal core logic from the 5V UVDD. It derives its
reference from the VBG Generator.
VDD must be buffered externally by a 220nF ceramic capac-
itor in parallel with a 10uF tantalum capacitor.
This module is permanently enabled except during power
saving modes. A certain set-up time has to elapse after
6.4.3. VDD Auxiliary Regulator
The low-power VDD Auxiliary Regulator generates a
reduced supply voltage for the core logic from the 5V UVDD.
6.4.4. FVDD Regulator
The FVDD Regulator generates the 3.3V FVDD supply volt-
age for the external Flash memory device from the 5V
UVDD. It derives its reference from the VBG Generator.
FVDD must be buffered externally by a 470nF ceramic
capacitor in parallel with a 3.3uF tantalum capacitor.
This module is permanently enabled except during power
saving modes. A certain set-up time has to elapse after
6.4.5. ALARM Comparator
The Alarm Comparator on the pin RESETQ allows the detec-
tion of a threshold higher than the reset threshold. An alarm
interrupt can be triggered with the output of this comparator.
To obtain a result that is independent from UVDD, the level
of pin RESETQ is compared to the VBG reference voltage.
The comparator features a small built-in hysteresis. The out-
put constitutes the RESETQ/ALARM Interrupt Source and
must be enabled by setting flag ANAU.EAL. Please refer to
section 6.5.1. for functional details.
58
Pulse Width Modulator 7
On
Off
Pulse Width Modulator 5
On
Off
Pulse Width Modulator 3
On
Off
Pulse Width Modulator 1
On
Off
June 12, 2003; 6251-579-1PD
IRQ
r/w1:
r/w0:
FIQ
r/w1:
r/w0:
CPUM
Clock selection for CPU and peripheral modules (Section
“CPU and Clock System”). Change CPUM by 32-bit access
only.
RESET and ALARM Comparators and the UVDD Supply
Supervision.
This module is permanently enabled except during power
saving modes.
power-up of UVDD for VDD to stabilize. During this time, the
Supply Supervision (cf. 6.4.7.) generates a Power-On Reset.
An overload condition in the regulator (current or voltage
drop-out) generates an immediate Reset and is stored in flag
ANAU.VE. The immediate overload signal may be routed to
the LCK special output by selection in field ANAU.LS.
This module is enabled only during IDLE mode, where no
clocked operation is required.
power-up of UVDD for FVDD to stabilize. During this time,
the Supply Supervision (cf. 6.4.7.) generates a Power-On
Reset.
An overload condition in the regulator (current or voltage
drop-out) generates an immediate Reset and is stored in flag
ANAU.FVE. The immediate overload signal may be routed to
the LCK special output by selection in field ANAU.LS.
The interrupt source output is routed to the Interrupt Control-
ler logic. But this does not necessarily select it as input to the
Interrupt Controller. Check section “Interrupt Controller” for
the actually selectable sources and how to select them.
The alarm interrupt is a level triggered interrupt. The interrupt
is active as long as the voltage on pin RESETQ remains
between the two thresholds of the ALARM and the RESET
comparator.
IRQ Interrupt Controller
Enabled
Disabled
FIQ Interrupt Controller
Enabled
Disabled
CPU Mode
PRELIMINARY DATA SHEET
Micronas