CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 95

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
The ISN has to be enabled (E=1) and programmed to the
desired priority (PRIO>0). Setting the pending flag P by SW
generates an interrupt. This interrupt will be processed as
soon as possible. When the CPU responds to the interrupt
request and jumps to the corresponding ISR, the pending
flag is cleared automatically.
11.5.2.1. Delayed Interrupt
Any ISN which is not used by the connected peripheral mod-
ule can be used for implementing the delayed interrupt
mechanism for an operating system. The ISN has to be
enabled (E=1) and programmed to priority 1 (the lowest pri-
ority which can generate an interrupt). Setting the pending
flag P by OS-SW within a higher priority interrupt service rou-
tine generates a delayed interrupt, which is processed after
all higher priority interrupts are finished.
11.5.3. Polling
Polling means that the pending flag P is observed by SW. Set
by the corresponding interrupt source, the SW recognizes
the P flag to be set, calls the corresponding routine and
clears the P flag. The ISN should be disabled (E=0), other-
wise unwanted IRQs would be generated.
11.5.4. Operating Nested Interrupts
Nested interrupt service routines use common data
resources. Every routine, which may have interrupted a lower
priority routine, has to save common data resources upon
interrupt entry and restore them before returning to the inter-
rupted routine. This is efficiently done by an entry and an exit
sequence which are enclosing the interrupt service routine.
11.5.4.1. Interrupt Entry Sequence
The IRQ disable flag I in the core register CPSR is set after
an IRQ, thus disabling further IRQs. Before the interrupt is
enabled again, the user has to take the following steps:
1. For direct vectoring: Jump to the corresponding interrupt
service routine by loading the first element from the vector
table into the program counter by an LDR instruction.
2. Save Link Register (R14), SPSR and working registers to
stack.
3. For delayed vectoring: Jump to the corresponding interrupt
service routine by loading the first element from the vector
table into the program counter an LDR instruction.
4. Clear CPSR.I to re-enable IRQs.
Now the actual application ISR can start.
11.5.4.2. Interrupt Exit Sequence
Before returning, it is necessary to clear the interrupt cause.
Upon exit from an ISR some actions have to be taken without
being interrupted:
1. Set CPSR.I to disable further IRQs.
2. Restore Link Register (R14), SPSR and working registers
from stack.
3. Generate the signal IExit by performing a word write by an
STR instruction to the interrupt exit address at [VTB]+0x100.
4. Returning to the interrupted routine has to be done by an
instruction, which simultaneously writes the PC (R15) and
CPSR with the values in R14 and SPSR (e.g. SUBS
PC,R14_irq,#4).
Micronas
June 12, 2003; 6251-579-1PD
11.5.5. Default Vector
Any read access to vector table address [VTB] will deliver the
default vector, but will not generate IAck as long as the com-
parator output is inactive or the priority output of the priority
encoder is zero. Due to this the default vector ISR runs with
the priority of the interrupted routine. This is the only ISR
which could be interrupted by itself. As long as this default
vector ISR is not programmed reentrant, interrupts should
not be re-enabled by clearing the I flag of the CPSR. No IExit
shall be generated on interrupt exit by writing to
[VTB]+0x100 because there was no IAck at interrupt entry.
Unintentional inactivation of an active comparator output sig-
nal can be caused by modifying the ISN which is the only
source for the momentary active nIRQ output. This can be
done by disabling (E=0), or clearing the P flag, or lowering
the priority of this ISN. Those actions may lead to a default
vector interrupt.
11.5.6. Debugger
Unintentional access to vector table addresses [VTB] and
[VTB]+0x100 can result in malfunction of the interrupt sys-
tem (HW and SW). If it is necessary, for instance, to dump
the vector table, there are two ways to do this without gener-
ation of IAck or IExit:
The first way is to clear the flag CRI.TE which controls the
vector table logic. Clearing it disables HW actions on access-
ing above addresses. But ensure that no interrupts are possi-
ble while TE is disabled.
The second way is to access above addresses by byte or half
word operations only. The HW actions are only generated by
word access. Disabling interrupts is not required in the latter
case.
11.5.7. Critical Code
Critical code is a sequence of instructions which must not be
interrupted, because it modifies common data resources.
Protection from being interrupted can be achieved by dis-
abling interrupts during critical code. There are several ways
of doing this:
11.5.7.1. ARM core’s Interrupt Disable Flag I and F
The ARM core itself provides the interrupt disable bits I and F
in the program status register CPSR.
The control bits of the CPSR (I, F and others) can be SW
altered only when the processor is in a privileged mode.
ARM recommends to modify the CPSR by a read-modify-
write instruction sequence in order to leave the reserved bits
unchanged.
The interesting case is when an interrupt comes in during
execution of the MSR instruction. The core commits to taking
an interrupt before the instruction being executed completes.
Therefore even though an MSR instruction may have written
to the CPSR to disable interrupts, the interrupt will still be
taken. A NOP between the MSR instruction and the first
instruction of the critical code is not necessary. If an interrupt
occurs during an MSR instruction, it will return to the instruc-
tion immediately following the MSR.
MRS
ORR
MSR
r0,cpsr
r0,r0,#I_Bit
cpsr_c,r0
;disable interrupts
CDC 32xxG-C
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