SDA9589X Micronas, SDA9589X Datasheet
SDA9589X
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SDA9589X Summary of contents
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Edition Feb. 28, 2001 6251-562-1PD PRELIMINARY DATA SHEET SDA 9489X PIP IV Advanced SDA 9589X SOPHISTICUS High-End Picture-In-Picture ICs ...
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... A maximum of 324 luminance and 2x81 chrominance pixels per line are stored in the memory. The PiP supports split-screen applications as well as multi-PiP display. Type SDA 9489X SDA 9589X Micronas Preliminary Data Sheet P-DSO28-1 Package P-DSO28-1 P-DSO28-1 CMOS ...
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... Inset Picture Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.8.5 Parent Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.8.6 Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.8.7 Automatic Brightness Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.9 On Screen Display (OSD .35 4.9.1 Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.9.2 Character Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.9.3 Character and Character Background Color . . . . . . . . . . . . . . . . . . . . . .36 4.10 DA-Conversion And RGB / YUV Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.10.1 Pedestal Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.10.2 Contrast, Brightness and Peak Level Adjustment . . . . . . . . . . . . . . . . . .38 Micronas Preliminary Data Sheet -3 ...
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... Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 I2C Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3 I2C bus Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.4 I2C Bus Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9 Recommended Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Micronas Preliminary Data Sheet -4 ...
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... pictures of 1/9th size (2 still and 1 moving) – Display on VGA and SVGA screen (f – 8 different read frequencies for 16:9 compatibility – Line doubling mode for progressive scan applications 1) SDA 9589X only Micronas Preliminary Data Sheet 1) , multistandard color decoding, PLL for 1) alternatively ...
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... I C-Bus control (400 kHz) • High stability clock generation • PDSO 28-1 package (SMD) • Full SDA 9488X and SDA 9588X backward compatibility • SDA 9388X / SDA 9389X pinout compatibility • 3.3V supply voltage (5V input capable) Micronas Preliminary Data Sheet Features 1-6 ...
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... SDA 9489X SDA 9589X 2 Pin Configuration XIN XQ HSP VSP SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW Figure 2-1 Pinning Figure 2-2 Package Outlines Micronas CVBS1 1 28 VREFM 2 27 CVBS2 3 26 VREFL 4 25 CVBS3 5 24 VSSA1 6 23 VDDA1 7 22 VREFH 8 21 ...
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... CVBS2 I/ana 27 VREFM I/O 28 CVBS1 I/ana I= Input / ana=analog / O= Output / TTL=Digital (TTL) / S=Supply voltage Table 2-1 Pin Description Micronas Description crystal oscillator (input) or external clock input crystal oscillator (output) horizontal sync for parent channel vertical sync for parent channel 2 I C-bus data 2 I C-bus clock ...
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... SDA 9489X SDA 9589X 3 Block Diagram DEMUX MUX Figure 3-1 Block Diagram Micronas DUV/DCHR DCVBS/DY Preliminary Data Sheet Block Diagram 3-9 ...
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... All signal are clamped and AD-converted with an amplitude resolution of 8bit. CVBS and Y signals are clamped to the sync bottom whereas U/V and C signals are clamped to their mid-level during blanking. Inset Video HD CLMPIST CLAMPI CLMPID Figure 4-1 Clamping timing Micronas 2 C bus (CVBSEL). CVBS2 and CVBS3 Input CVBS2 CVBS3 CVBS CVBS Y (VBS) C CVBS ...
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... Its levels correspond to the CVBS levels except for the missing color and burst. After A/D conversion the video part is clamped to its black value and is amplified to 224 digital steps. The nominal signal levels ensure correct brightness and saturation. The YUV signal levels conform to the ITU 601 recommendation. Micronas Automatic Gain Control Characteristic 4 6 ...
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... Conversion Range 0.5V ... 1.2V ... 1.5V Table 4-2 ADC conversion range and required input signal voltage Micronas 255 224 128 32 0 255 240 212 75% V 128 Signal Signal Range Range CRYC SRY SRC 0.42V pp pp ... ... ...
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... For getting the chrominance information the digitized video signal is multiplied with the regenerated color subcarrier once in-phase and once phase-shifted by 90°. After lowpass filtering digital UV is available for PAL and NTSC. The subcarrier is regenerated Micronas Preliminary Data Sheet PAL-N PAL-M ...
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... Alternatively the color-killer can be bypassed and the color can be switched on or off under all conditions (COLON). By setting ACCFIX, the automatic chroma control is disabled and set to a default value. Micronas 5 2.5 IFCOMP = ’00’ ...
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... IRE’). As for some applications a black offset is not desired, controlling may be done using LMOFST. The positive or negative offset is added to the Y signal before scaling. Micronas color killed at damping ...
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... HSHRINK and VSHRINK, which allows correct aspect ratio for multistandard applications (50/60 Hz mixed mode, (S)VGA). For main decimation factors, the stored number of pixel and lines are listed in the following tables. Micronas Preliminary Data Sheet Processed signal BLACK value BLANK value ...
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... Automatic zooming is only possible in frame mode. Being in field mode, the picture size remains stable until frame mode occurs or until the internal counter reaches the desired Micronas Preliminary Data Sheet System Description PIP Pixel per line ...
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... Table 4-7 Number of stored lines per field dependent on VSHRNK Micronas 525 lines 625 lines 2 108 0 2 2,03 106 1 2 4,13 2,08 104 2 2 4,25 2,13 102 3 2 4,41 2,16 100 4 2 4,56 2 4,72 2, 4,88 2 5,06 2, ...
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... Number of stored pixel per line dependent on HSHRNK 4.6.3 Horizontal And Vertical Fine Positioning All picture sizes are pre-centered inside the frame. In addition, if necessary the vertical and horizontal acquisition area can be shifted by VFP for vertical and HFP for horizontal direction. Micronas 0 1 3,00 216 0 ...
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... For split screen applications two selectable ’double window’ modes in which one half of the picture is generated by the ’Sophisticus’/’PIP IV Advanced’ can be used. The split screen mode can be selected by two possible combinations of DISPMOD. Figure 4-7 Double window mode 1.5 (left picture) and mode 1 (right picture) Micronas Size Picture configuration single PIP mode ...
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... If a display mode is chosen that is not implemented, the PIP insertion is switched off automatically (PIPON = ’0’). The sizes of the partial pictures correspond to the sizes of the inset pictures of the single PIP modes. Micronas Preliminary Data Sheet maximum number of pictures (including one live picture) ...
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... Hz) video sources are applied to inset and parent channel, joint-line free frame mode display is possible. This means that every incoming field is processed and displayed by the SDA 9589X/SDA 9489X processors. The result is a high vertical and time resolution. For this purpose the standard is analyzed internally and frame mode display is blocked Micronas Size Picture configuration ...
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... Synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals connected to the pin HSP for horizontal synchronization and pin VSP for vertical synchronization. HSPINV or VSPINV respectively allow an inversion of the expected signal polarity. Micronas number of FMACTI 310...315 0 290 ...
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... By means of VSPNSRQ, vertical noise suppression is switched off. A great variety of combinations of inset and parent frequencies are possible. The following table shows some constellations. Micronas Preliminary Data Sheet =151 (75) ←s VSPDEL max field 1 window (32) ← ...
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... HSP and VSP. If the sequence ∼ϒ∼ϒ is detected, the field mode will be activated again. Continous switching between these modes is possible, resulting in continous switching between field- and frame mode. Micronas frame correct aspect ...
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... Table 4-14 Examples of supported parent signals Micronas T T lines Hact dot ( ← ← s) active (MHz) 64.0 52.0 625/ 13.5 576 63.6 52.7 525/ 13.5 488 32.0 26.0 625/ 27 576 31.8 26.4 525/ ...
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... For a single-PiP, the number of displayed lines depends on the selected picture size and on the signal standard. For multi picture display, the number of displayed lines depends on the selected picture size and on the signal standard of the parent signal. Additionally, a standard can be forced by DISPSTD. Micronas Expected input signal signal interlace 100 or 120 Hz signals interlace ...
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... POSHOR and POSVER. The corner positions can be centered coarsely on the screen with POSOFH and POSOFV. Depending on coarse position, one PIP corner remains stable when changing the picture size. Micronas Display Standard PIP depends on detected inset standard (single pip) PIP depends on detected parent standard (multi display) ...
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... CPOS. Thereby the size of the visible picture-part is continuously increased and decreased respectively. During this procedure the frame is shown with its chosen widths. 3 different wipe in / out time periods or ’no wipe’ are programmable via WIPESPD. The wipe algorithm always works in horizontal and vertical direction. Micronas Reference increasing corner of PiP ...
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... This value provides a good compromise between sharpness impression and annoying aliasing. The characteristic for all possible settings is shown in fig. (4-12). The emphasized frequency depends on the adjusted decimation. The gain maximum is always located before the band-limit ensuring optimal picture impression. Micronas wipe out CPOS='01' CPOS='00' ...
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... Table 4-18 RGB matrices characteristics The color saturation can be adjusted with SATADJ register in 16 steps between 0 and 1.875. Values above 1.0 may clip the chrominance signals. Micronas 0.2 0.3 0.4 normed frequency Angles (G-Y) (B-Y) (R-Y) 0 0.608 0 95 0.608 0 105 ...
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... There is no shift of the inset picture position if the inset frame width is modified. character haracter luminance frame color frame rame color Figure 4-14 Selectable picture configurations Micronas character background transparent c har. background luminance semi-transparent PiP Picture b ackground p icture shades ...
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... The phase of the output signals is locked to the rising edge of the horizontal sync pulse. The frequency varies in a certain range to ensure correct aspect ratio for 16:9 applications depending on HZOOM. The horizontal and vertical scaling can be used for all display frequencies. Micronas displayed displayed lines (50Hz) ...
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... Therefore a detection circuit reduces the brightness of the inset picture when the average brightness is above a selectable threshold. After bright picture content has disappeared, the initial brightness reappears. The threshold is adjustable via ABRTHD and the speed via ABRSPD. Both settings have to be selected for parent system accordingly. Micronas desired required PiP format parent ...
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... In this case the address is increased automatically. The 7 bit address consists of two parts: the 4 MSBs are used to chose one of the partial pictures and the 3 LSBs to select one of the 5 characters per block. Micronas Preliminary Data Sheet System Description 4-35 ...
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... VGA applications. The position and the length of the blanking pulse as well as the clamping pulse are adjustable (CLPPOS, CLPLEN). If READD is set to ’1’ (100Hz mode), all pulses are shortened by one half. HZOOM influences the adjustment range of Micronas RGBINS='10' RGBINS='11' ...
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... The pedestal level adjustment controlled by I enables the correction of small offset errors, possibly appearing at the successive blanking stage of RGB processor. This adjustment has an effect on the setup level during the active line interval of each channel like the brightness adjustment but has an Micronas 256 ← ...
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... BLKINVR = BLKINVB = ’0’ OUT1, 3 BLKLR = 15 BLKLB = 15 64 BLKLR = 0 BLKLB = 0 OUTFOR = ’0’ (RGB Mode) BLKLR = 15 BLKLB = 15 BLKLG = 15 BLKLR = 0 BLKLB = 0 BLKLG = 0 0 Figure 4-21 Pedestal level adjustment Micronas BLKINVR = BLKINVB = ’1’ OUT1, 3 BLKLR = 15 BLKLB = 15 64 BLKLR = 0 BLKLB = 0 OUT1 - 3 Preliminary Data Sheet System Description 4-38 ...
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... SLFIELD. If one or more XDS-class filter are activated, SLFIELD contains always ’1’. Additionally pin 10 (INT) may flag that new data is received. Default this pin is in tri-state mode to be compatible with Micronas' SDA9388X/9389X PIP devices. It can also be configured by IRQCON to output a single short pulse when new data is available or behave equal to DATAV ...
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... Message” THIS PROGRAM CONTAINS VIOLENT SCENES Figure 4-23 Possibilities of PiP blocking The Mosaic mode (MOSAIC) hides details of the picture by reduced sharpness and increased aliasing. The picture looks scrambled and is less perceptible. Micronas Preliminary Data Sheet “Blue Screen” System Description “Mosaic” 4-40 ...
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... SDA9589X SDA9589X H/V H Featurebox YUV YUV i.e.SDA 9400 1H 2H CVBS (Y/C, YUV) H/V H Featurebox YUV i.e. SDA 9400 YUV 1H 2H Preliminary Data Sheet Application Examples SDA9589X SDA9589X SDA 9400 additional 2f sources H Backend i.e. SDA9380 IN1-3 SDA9589X HSP/VSP I2C OUT1-3 additional 2f sources H Backend i.e. SDA9380 5-41 ...
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... SDA 9489X SDA 9589X smaller than 1/9. The output of an OSD/Text processor may be fed to the RGB switch of the SDA 9589X/SDA 9489X. Micronas Preliminary Data Sheet Application Examples 5-42 ...
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... WRITE S 1101x110 A Subaddress A READ S 1101x110 A Subaddress A Sr 1101x111 A Data Byte Start condition / Sr Repeated start condition / A: Acknowledge / P: Stop condition / Write operation is possible at registers 00h-21h only, read operation is possible at registers 28, 2Ah-2Ch only. An automatic address increment function is implemented. Micronas ...
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... CONADJ3 CONADJ2 CONADJ1 CONADJ0 12h BRTADJ3 BRTADJ2 13h TRIOUT REFINT 14h PKLR7 PKLR6 15h PKLG7 PKLG6 16h PKLB7 PKLB6 Micronas Data Byte CPOS0 YUVSEL READD VFP1 VFP0 HFP3 FREEZE MOSAIC SIZEHOR1 SIZEHOR0 SIZEVER1 SIZEVER0 PIPBG1 PIPBG0 FMACTP VSPNSRQ VSPDEL4 ...
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... FRMMD PIPSTAT 29h (reserved) (reserved) 2Ah DATAA7 DATAA6 2Bh DATAB7 DATAB6 2Ch After power on the grey marked data bits are set to '1', all other to ‘0‘. Micronas Data Byte BGY1 BGY0 FRY3 BGU1 BGU0 FRU3 BGV1 BGV0 FRV3 SATADJ1 SATADJ0† ...
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... READD D3 double read frequency for compatibility with systems that use 2fH (e.g.100 Hz, progressive) 0 PIP display with single read frequency and 2x oversampling 1 PIP display with double read frequency Micronas Preliminary Data Sheet PiP on Coarse position YUV Select Read Double Mode I2C Bus 6-46 ...
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... Subaddress 02h POSVER D7-D0 vertical position adjustment of the PIP in steps of 1 lines shift direction depends on the coarse positioning of the picture Micronas Preliminary Data Sheet Progressive Scan Enable Field Select Horizontal Picture Position Vertical Picture Position ...
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... PIP display is always in 625 line mode 1 0 PIP display is always in 525 line mode 1 1 freeze last detected display standard and size Micronas Preliminary Data Sheet Horizontal Fine Positioning Vertical Fine Positioning Display Standard I2C Bus Note values refer to the undecimated ...
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... SIZEHOR D3 D2 horizontal decimation 0 0 reduction = reduction = reduction = reduction = 6 SIZEVER D1 D0 vertical decimation 0 0 reduction = reduction = reduction = reduction = 6 Micronas Preliminary Data Sheet Freeze Picture Mosaic Mode Horizontal Size Vertical Size I2C Bus 6-49 ...
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... D1 D0 selects the parent (display) clock frequency 27.34 MHz 20.25 MHz 35.27 MHz 25.43 MHz 26.67 MHz 20.63 MHz 34.17MHz 28.04 MHz Micronas Force Parent Standard PIP Background Display Frame Mode Activation Parent Horizontal Zoom Preliminary Data Sheet I2C Bus 6-50 ...
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... FRSEL D7 selects between the normal frame and the shaded frame 0 normal frame 1 shaded frame with 3D impression Micronas Horizontal Sync Pulse Inversion Vertical Sync Pulse Inversion Vertical Sync Pulse Noise Reduction Vertical Sync Pulse Delay D0 delay of the vertical sync pulse in steps of 128 parent clocks ...
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... FSW possible (priority of FSW input external insertion with FSW possible (priority of PIP) Micronas Inner Frame activation Vertical Picture Size Reduction Frame Width Horizontal Frame Width Vertical RGB Insertion Preliminary Data Sheet I2C Bus ...
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... Subaddress 09h POSCOR D7 activates correction of display position 0 position correction disabled 1 position correction enabled Micronas Preliminary Data Sheet Vertical Blanking Select Down Select Delay Position Correction I2C Bus 6-53 ...
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... ADC overflow only 1 1 AGC fixed (gain depends on AGCVAL) Micronas Display Mode Clamping Delay delay of the clamping pulse for the external RGB/YUV inputs in steps of 8 parent clock periods no delay (0) maximum delay, 256 clock periods of parent ...
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... CVBS2 1 0 Y/C (Y@CVBS2 / C@CVBS3 CVBS3 CLMPID D5 D4 adjusts duration of clamping pulse for ADC (inset channel 0.5← 0.9← 1.2← 1.5←s Micronas Preliminary Data Sheet Automatic Gain Control Value No Signal Behavior CVBS Select Clamping Duration I2C Bus 6-55 ...
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... Micronas Preliminary Data Sheet Clamping Pulse Start Luminance Offset Inset PLL Time Constant Noise Reduction Inset PLL Note may cause trouble for VCR signals I2C Bus ...
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... SECAM, PAL B/G, PAL60, NTSC4 ignore PAL-M /PAL-N / NTSC ignore PAL-M / PAL-N / NTSC4.4 / PAL60 LOCKSP D2 sets the speed of the color standard recognition 0 medium 1 fast Micronas Y/C Delay Color Standard Color Standard Exclusion Standard Identification Speed Preliminary Data Sheet I2C Bus 6-57 ...
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... Filter2 1 1 Filter3 COLON D3 disable color killer 0 color killer active 1 color forced on Micronas Preliminary Data Sheet Color Killer Threshold Note only valid if color killer active (COLON=’0’), values are approximative Burst Gate Position SECAM Identification Level Deemphase Selection Color On I2C Bus ...
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... HUE Micronas Disable Automatic Chroma Control Chroma Bandwidth SECAM remark small adjusts chroma bandwidth medium wide IF-Compensation Filter Hue Control D0 phase of color subcarrier for NTSC 0 -44.8° 0° 43.4° Preliminary Data Sheet ...
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... OUT1-OUT3 nominal contrast .. +30% contrast increase Micronas Satellite Noise Reduction Frame Mode Activation Inset Chroma PLL Off Color Subcarrier Adjustment D0 color subcarrier frequency fine adjustment 0 max. negative deviation (-150 ppm) ... 1 default (for nominal crystal frequency ...
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... Subaddress 13h TRIOUT D7 sets OUT1-OUT3 to tristate mode (high resistance) 0 normal operation, outputs are active 1 pins OUT1-3 are in tri-state mode Micronas Preliminary Data Sheet Blanking Level Red Brightness Adjustment Blanking Level Green Tristate Output I2C Bus 6-61 ...
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... adjusts the pedestal level of the OUT3 channel in steps of 0.5LSB pedestal .. +7.5LSB offset Micronas Preliminary Data Sheet Refresh Intervall Note let it to this default value Blanking Inversion Red Blanking Inversion Blue Blanking Level Blue I2C Bus 6-62 ...
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... Subaddress 15h PKLG Micronas Peak Level Red peak to peak output voltage of the OUT1 channel 0 ... ... 1 Peak Level Green peak to peak ...
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... BGY D5-D4 adjusts the Y background color component the values gives the two MSBs of the Y background signal FRY D3-D0 adjusts the Y frame color component the value gives the 4 MSBs of the Y frame signal Micronas Peak Level Blue peak to peak output voltage of the OUT2 channel ...
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... Subaddress 19h BGFRC D6 selects background color table or frame color table for background color 0 background color according to BGY, BGU, BGV 1 background color according to FRY, FRU, FRV Micronas Preliminary Data Sheet Output Format UV Polarity Background Color U Frame Color U Background Frame Color I2C Bus 6-65 ...
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... YPEAK adjusts luminance peaking peaking recommended value strongest peaking YCOR D0 suppresses noise introduced by peaking 0 coring off 1 1LSB coring Micronas Preliminary Data Sheet Background Color V Frame Color V Color Saturation Adjustment Y Peaking Adjustment Y Coring Enable I2C Bus 6-66 ...
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... Subaddress 1Ch UVSEQ D7 changes the UV multiplex sequence 0 U and V are correct 1 U and V are exchanged Micronas XDS Class Select Closed Caption XDS-Primary Filter (Class) transparent, no filtering ’Current’ class selected ’Future’ class selected ’Channel’ class selected ’Miscellaneous’ class selected ’ ...
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... V-pulse (neg. polarity inset field inset clamping pulse (neg. polarity) Micronas Multi-PIP Background Data Service Select Select Line Number remark WSS Closed Caption Closed Caption WSS Interrupt Request Pin Configuration remark pulse length is approximately 2←s ...
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... POSOFH ... ... Micronas PIP Blank PAL ID Level Position Offset Vertical Position Offset Horizontal horizontal position offset in steps of 16 pixel -256 pixel 0 pixel +240 pixel Preliminary Data Sheet I2C Bus 6-69 ...
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... Micronas Vertical Shrink changes the vertical size in steps of 2 lines no shrink, picture size according to SIZEVER max. possible shrink Horizontal Shrink changes the horzontal size in steps of 4 pixel no shrink, picture size according to SIZEHOR max. possible shrink ...
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... SDA 9589X/9489X applications 1 inner frame suited for usage of dual SDA 9589X/9489X applications Micronas PIP Highlighting Automatic Brightness Reduction Threshold Automatic Brightness Reduction Speed Inner Frame Modification Preliminary Data Sheet ...
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... Micronas Display Mode selects the single PIP modes, Multi- PIP modes or Double-Window mode Single PiP mode OSD only mode Wipe Speed Continuos Zoom Enable Continuos Zoom Speed 1 step means 20 pixel and 8 ...
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... Micronas Write Position Note position depends on display mode (DISPMOD) Character Frame Color Character Double Height and Width Character Luminance Note valid only if CHRFRC = ’0’, character chrominance is 0 IRE Preliminary Data Sheet ...
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... CHRBGY semi-transparent mode (black&white semi-transparent mode (colored) Subaddress 26h OSDON D7 switches OSD on 0 OSD off 1 OSD on Micronas Character Background Luminance Character Background On Note not possible in case of active background in PiP OSD On Preliminary Data Sheet I2C Bus 6-74 ...
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... CHRCOD D6-D0 character code, see Appendix Subaddress 28h FRMMD D7 PIP displays field or frame mode 0 field mode, one field is repeated twice 1 frame mode, both fields are displayed Micronas Character Address D1 D0 No. picture No. character ... ... 0 0 ...
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... STDET detected color standard nonstandard or standard not detected NTSC PAL NTSC44 PAL60 PAL SECAM PAL-B/G Micronas Preliminary Data Sheet PIP Status Inset Synchronization Status Color Killer Status Standard Detection I2C Bus 6-76 ...
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... SDA 9489X SDA 9589X Subaddress 2Ah DATAA D7-D0 first word of sliced data MSB LSB Subaddress 2Bh DATAB D7-D0 second word of sliced data MSB LSB Subaddress 2Ch DEVICE Micronas PIP SDA 9488X (PIP IV Basic SDA 9489X (PIP IV Advanced SDA 9588X (OCTOPUS) ...
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... I 1 new data received and available in DATAA and DATAB SLFIELD D0 DATAA and DATAB are from 0 first field 1 second field Micronas Data Valid data available Sliced Data Field Number Preliminary Data Sheet I2C Bus 6-78 ...
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... SDA 9489X SDA 9589X 7 Pin Description pin 1 (XIN) 2 (XQ) XIN 3 (HSP) 4 (VSP VSP 5 (SDA) 6 (SCL) SDA SCL 9 (I2C) Micronas schematic VDD VDD VDD VDD slope control VDD I2C Preliminary Data Sheet Pin Description remark crystal oscillator, input can be used for ...
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... SDA 9489X SDA 9589X pin 10 (INT VDD (IN1 IN2 IN3) IN1 IN2 IN3 14 (FSW) FSW 15 (SEL) Micronas schematic VDD INT + - VDD VDD SEL Preliminary Data Sheet Pin Description remark clamped RGB/YUV video inputs, if not used let open or connect with 10nF to ...
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... SDA 9589X pin 16 (OUT3) 17 (OUT2) 18 (OUT1) 21 (VREFH) VDD 25 (VREFL) 27 (VREFM) VREFH 24 (CVBS3) VDD VDD 26 (CVBS2) CVBS1 28 (CVBS1) CVBS2 CVBS3 Micronas schematic UT1 O UT2 O UT3 + - VDD VDD VREFM VREFL Preliminary Data Sheet Pin Description remark RGB/YUV video outputs reference voltage for ...
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... Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Micronas Absolute Maximum Ratings Symbol Limit Values min ...
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... Inset Input: CVBS1, CVBS2, CVBS3 Horizontal Frequency Horizontal Frequency Amplitude of synchronization pulse length of horizontal synchronization puls length of vertical synchronization puls chroma amplitude Input Coupling Capacitors CVBS Source Resistance Micronas Recommended Operating Range Limit Values min. typ. 3.15 3.3 DDxx 15.000 15.625 ...
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... I/O pins. SCL Clock Frequency Inactive Time Before Start Of Transmission Set-Up Time Start t SU;STA Condition Hold Time Start t HD;STA Condition SCL Low Time Micronas Recommended Operating Range Limit Values min. typ. Vi 0.5 1 1.05 1.11 REFL 1.81 1.91 REFM 3 ...
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... Spike Duration At Inputs Low-Level Output Current Digital To Analog Converters (7-bit):OUT1, OUT2, OUT3 Load resistance Load capacitance Crystal Specification: XIN, XQ Frequency Maximum Permissible Frequency Deviation αf/f Recommended Permissible Frequency Deviation Micronas Recommended Operating Range Limit Values min. typ. t 0.6 HIGH 100 20 ...
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... SDA 9489X SDA 9589X Parameter Symbol Load Capacitance Series resonance resistance Motional capacitance Parallel capacitance In the operating range the functions given in the circuit description are fulfilled. Micronas Recommended Operating Range Limit Values min. typ Preliminary Data Sheet ...
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... Low-Level Input Voltage High-Level Input Voltage Delay FSW in -> SEL out I²C Inputs: SDA/SCL Schmitt Trigger Hysteresis I²C Input / Output: SDA (Referenced to SCL; Open Drain Output) Low-Level Output Voltage Low-Level Output Voltage Micronas Limit Values min. typ. I 180 210 DDtot ...
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... Current deviation Reference Voltage V Difference D.C. Differential Nonlinearity Crosstalk between CVBS Inputs Digital To Analog Converters (7-bit): Outputs OUT1, OUT2, OUT3 D.C. Differential Nonlinearity Full Range Output Voltage Full Range Output Voltage Micronas Limit Values min. typ. t 20+0. / -100 αCLE ...
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... Input Voltage Range Bandwith (-3dB) Gain Gain Difference RGB Crosstalk Between Inputs Crosstalk Between Inputs Isolation (off state) αCLPE Clamping Level Difference at Output Colordecoder/Synchronization and Luminance Processing Horizontal PLL pull-in- range Micronas Limit Values min. typ 400 αBRT α ...
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... Co Channel Distortion Max. permissible Noise The listed characteristics are ensured over the operating range of the integratd circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T voltage. Micronas Limit Values min. typ. α ...
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... SDA 9489X SDA 9589X 11 Diagrams Figure 11-1 Display mode 0 with picture sizes 1/4 and 1/9 Figure 11-2 Display mode 0 with picture sizes 1/16 and 1/36 Micronas Preliminary Data Sheet Diagrams 11-91 ...
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... SDA 9489X SDA 9589X Figure 11-3 Display mode 0 (with scaling) and display mode 11 Figure 11-4 Display mode 2 and 3 (all pictures with same content Figure 11-5 Display modes 4 and 5 Micronas Preliminary Data Sheet Diagrams 11-92 ...
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... SDA 9489X SDA 9589X 0 1 Figure 11-6 Display modes 6 and Figure 11-7 Display modes 8 and Figure 11-8 Display modes 9 and 10 Micronas Preliminary Data Sheet Diagrams 11-93 ...
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... Figure 11-9 Display modes 13 and Figure 11-10 Display modes 15 and Figure 11-11 Display modes 17 and 18 Micronas Preliminary Data Sheet Diagrams ...
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... SDA 9489X SDA 9589X Display mode 20 (Double Window 1) and 19 (Double Window 1.5) Figure 11-12 Combination of display modes 17/ 18 and 9/ 10 (dual PiP application) Figure 11-13 Display modes 19 and 20 (dual PiP application) Micronas Preliminary Data Sheet Diagrams 11-95 ...
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... Figure 11-14 OSD Character Set Micronas 0000100=04 0000101=05 0000110=06 0100000=20 0100011=23 0100001=21 0101111=2F 0110000=30 0110001=31 0110111=37 0111000=38 0111001=39 1000010=42 1000011=43 1000100=44 1001010=4A 1001100=4C 1001011=4B ...
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... SDA 9489X SDA 9589X CVBS 1 TUNER1 CVBS 2 CVBS 3 CVBS 1 TUNER2 Figure 11-15 General Application with 3 CVBS sources and Teletext-Processor CVBS 1 TUNER2 Figure 11-16 General Application with YUV source from DVD Micronas Teletext or OSD processor optional PIP FSW SEL R(V) G (Y) B(U) HSP ...
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... YPEAK = '111' 1/16 PiP frequency [MHz] YPEAK = '010' YPEAK = '100' YPEAK = '111' Figure 11-17 Characteristic (PAL) of luminance decimation filter for different peaking factors Micronas YPEAK = '010' YPEAK = '100' YPEAK = '111 ...
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... YPEAK = '111' 1/16 PiP frequency [MHz] YPEAK = '010' YPEAK = '100' YPEAK = '111' Figure 11-18 Characteristic (NTSC) of luminance decimation filter for different peaking factors Micronas YPEAK = '010' YPEAK = '100' YPEAK = '111 ...
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... PiP 1/9 PiP 1/16 PiP 1/36 PiP 0.25 0.5 0.75 1 1.25 1.5 frequency [MHz] 1/4 PiP 1/9 PiP 1/16 PiP 1/36 PiP Figure 11-19 Characteristic of chrominance decoder filter (small, medium and narrow) Micronas 1.75 2 2.25 2.5 0 0.25 0.5 1/4 PiP 1/9 PiP 1/16 PiP 1/36 PiP 3 6 1.75 2 2.25 2.5 Preliminary Data Sheet Diagrams ...
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... L1 10← 10n 10← J1 DEh I2C Address D6h C5 10n RVIN C6 10n GYIN C7 10n BUIN FSW exact value depends on crystal specification Micronas C18 10n C19 10n C20 10n 10n XIN CVBS1 C9 1← VREFM 3 26 ...
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... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...