CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 62

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
6.4.6. RESET Comparator
As long as the Reset Comparator on the pin RESETQ
detects the low level, the overall IC is reset except the PSM/
RTC.
To obtain a result that is independent from UVDD, the level
of pin RESETQ is compared to the scaled down VBG refer-
ence voltage. The comparator features a built-in hysteresis.
6.4.7. Supply Supervision
When UVDD drops below a level VREFPOR of approx. 2.8V,
or when the internal VDD or FVDD Regulators detect an
overload condition, this module generates a Power-On reset
signal POR that is routed to the Reset Logic.
6.4.8. XTAL Oscillator
The XTAL Oscillator generates a 4 to 5 MHz reference signal
from an external quartz resonator, cf. section “Electrical char-
acteristics” for quartz data.
A reset sets the module to START-UP mode, where, at the
expense of a higher current consumption, marginal quartzes
receive more drive to ease start-up of oscillation.
After start-up of the CPU program, register SR0.XTAL may
be cleared by SW to set the XTAL Oscillator to RUN mode,
where current consumption is at its standard level.
6.4.9. UVDD Analog Registers
EAL
r/w1:
r/w0:
LS
w0:
w1:
6.5. Reset Logic
6.5.1. Alarm Function
The Alarm Comparator on the pin RESETQ allows the detec-
tion of a threshold higher than the reset threshold. An alarm
interrupt can be triggered with the output of this comparator.
The intended use of this function is made, when a system
uses a 5V regulator with an unregulated input. In this case,
the unregulated input, scaled down by a resistive divider, is
fed to the RESETQ pin. With falling regulator input voltage
this alarm interrupt is triggered first. Then the reset threshold
is reached and the IC is reset before the regulator drops out.
60
r/w
ANAU
EAL
0
7
x
6
-
LCK Output Select
Enable RESET/ALARM Interrupt Source
output
Enabled.
Disabled.
PLL Lock Signal.
VDD Regulator Error.
Analog UVDD Register
0
5
LS
0
4
LE
0
3
x
2
-
FVE
0
1
June 12, 2003; 6251-579-1PD
VE
0
0
Res
During power saving modes, the comparator function is not
available and is bypassed by a simple CMOS Schmitt input.
Full CMOS input levels (V
UV
Please refer to sections 6.5.2. and 6.5.3. for functional
details.
Refer to section 6.5.2.1. for more details.
This module is permanently active except during power sav-
ing modes.
For operation at UVDD levels between 3.5V and 4.5V, con-
tinuous operation of the module in START-UP mode may be
necessary, to guarantee sufficient drive to the connected
quartz.
Switching between START-UP and RUN modes must not be
done in CPU modes PLL or PLL2, as this might lead to
unpredictable behaviour of the clock system.
This module is permanently active except during power sav-
ing modes, where continued operation may be selected for
STANDBY and IDLE modes in register OSC.XM.
w2:
w3:
LE
w1:
w0:
FVE
r1:
r0:
w1:
w0:
VE
r1:
r0:
w1:
w0:
The time interval between the occurrence of the alarm inter-
rupt and the reset may be used to save process data to non-
volatile memory. In addition, power saving steps like turning
off stepper motor drivers may be taken to increase the time
interval until reset.
6.5.2. Internal Reset Sources
During CPU-active modes, this IC contains four internal cir-
cuits that are able to generate a system reset: watchdog,
supply supervision, clock supervision and FHR flag.
DD
0.3V) are thus required on this input in these modes.
FVDD Regulator Error.
BVDD Regulator Error.
LCK Enable
LCK signal at pin.
PFM1 output at pin.
FVDD Regulator Error Flag
Out of specification.
Normal operation.
Reset flag.
No action.
VDD Regulator Error Flag
Out of specification.
Normal operation.
Reset flag.
No action.
PRELIMINARY DATA SHEET
il
= UV
SS
0.3V and V
Micronas
ih
=