CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 119

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
17. Pulse Width Modulator (PWM)
A PWM is an auto reload down-counter with fixed reload
interval. It serves to generate a frequency signal with vari-
able pulse width or, with an external low pass filter, as a digi-
tal to analog converter.
This module is combined of two independently operatable
8bit PWMs which can be combined to a single 16bit PWM.
The number of PWMs implemented is given in table 17–1.
The “x” in register names distinguishes the module number
and can be 1, 3, 5, 7, 9, 11.
Fig. 17–1:
17.1. Principle of Operation
17.1.1. General
A PWM’s down-counter is clocked by its input clock and
counts down to zero. Reaching zero, it stops and sets the
output to LOW. A period input pulse reloads the counter with
the content of the PWM register, restarts it and sets the out-
put to HIGH.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
17.1.2. Hardware settings
The clock and period input frequencies are settable by HW
option (Table 17–1). There is one common source for both
8bit PWMs, one for clock and one for period, thus clock and
period are not independently selectable for the two 8bit
PWMs. For full resolution a clock to period frequency ratio of
256 (65536 in 16bit mode) is recommended. Should other
ratios be used, make sure that the combination of clock,
period and pulse width setting allow the PWM to generate an
output signal with a LOW transition.
Some of the PWM outputs share pins with outputs of other
modules. The output multiplexer is controlled by HW option
(Table 17–1).
Micronas
PxP
PxC
HW Option
SR1.PWMx
PWMC.P16x
period
clock
PWM Block Diagram
1
LSB
clk
en
8bit down counter
load
PWMx-1
8
ovf
0
1
June 12, 2003; 6251-579-1PD
1
1
0
MSB
Features
– Two 8bit or one 16bit pulse width modulator
– Wide range of HW option selectable cycle frequencies
17.1.3. Initialization
Prior to entering active mode, proper SW initialization of the
H-Ports and U-Ports assigned to function as PWMx outputs
has to be made (Table 17–1). The ports have to be config-
ured Special Out. Refer to “Ports” for details.
It has to be decided which PWM module shall work as one
16bit or as two 8bit PWMs. Selection has to be done via the
PWM control register PWMC as long as the PWM module is
disabled.
17.1.4. Operation
After reset, a PWM is in standby mode (inactive) and the out-
put signal PWMx is LOW.
For entering active mode, select the desired mode (8-/16bit
mode) and then set the respective enable bit (Table 17–1).
Then write the desired pulse width value to register PWMx
(write low byte first in 16bit mode). Each PWM will start pro-
ducing its output signal immediately after the next subse-
quent input pulse on its period input.
During active mode, a new pulse width value is set by simply
writing to the register PWMx. Upon the next subsequent
input pulse on its period input the PWM will start producing
an output signal with the new pulse width value, starting with
a HIGH level.
clk
en
8bit down counter
load
PWMx
8
ovf
S
R
S
R
CDC 32xxG-C
Q
Q
1
0
1
0
x = 1, 3, 5, 7, 9, 11
PWMx-1
PWMx
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