CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 105

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
14.3. Universal Port Registers
Eight U-Port registers are basically available for 9 U-Ports U0
to U8, each. Because some U-Ports are less than 8 pins
wide, not all of the described bits are available for every port.
Furthermore, the respective device’s pinning may require a
reduction in available U-Ports. See the respective pinning
table for details.
The general U-Port register model is given below.
L0 to 7
Select the mode of the corresponding port pins.
r/w1:
r/w0:
D0 to 7
w:
r:
SG0_0 to 7_3
w:
r:
In LCD mode, U-Port registers UxD, UxTRI, UxNS and
UxDPM store LCD segment information. Segment register
bits UxY.SGm_n contain the information for segment line m
during phase n, which controls segment m_n. Thus, register
bits
UxPIN.SG0_3 contain the complete information for segment
line 0 in U-Port x.
Please refer to Pin Assignment and Description for segment/
pin number assignment. Information about the usage of the
LCD Segment field will be found at the functional description
of the LCD Module.
T0 to 7
r/w1:
r/w0:
Micronas
r/w
r/w
r/w
r/w
r/w
UxMODE
UxD
UxTRI
SG7_0
SG7_1
7
7
L7
D7
T7
UxD.SG0_0,
0
0
1
7
SG6_0
SG6_1
6
L6
D6
6
T6
0
0
1
6
Output Tristate Flag 0 to 7
Port Mode Flag
Data Latch
Write latch.
Read latch.
Output driver is disabled (tristate)
Output driver is enabled
Port pin is in LCD mode.
Port pin is in Port mode.
SG5_0
SG5_1
Universal Port Mode Register
Universal Port x Tristate / Segment 1
Register
L5
Universal Port x Data / Segment 0
Register
D5
T5
5
5
0
0
Segment Data Latch
Write latch.
Read latch.
1
5
UxTRI.SG0_1,
SG4_0
SG4_1
L4
D4
T4
4
4
0
0
1
4
SG3_0
SG3_1
L3
D3
T3
3
3
0
0
1
3
SG2_0
SG2_1
L2
D2
T2
2
0
0
2
1
2
UxNS.SG0_2
SG1_0
SG1_1
L1
D1
T1
1
0
0
1
1
1
SG0_0
SG0_1
June 12, 2003; 6251-579-1PD
L0
D0
T0
0
0
1
0
0
0
and
Res
Port
LCD
Res
Port
LCD
Res
S0 to 7
r/w1:
r/w0:
D0 to 7
r/w1:
r/w0:
All U-Port pins may be switched into a Double Pull-down
Mode (DPM) by setting the appropriate DPMx flag, where
– the short circuit current I
– the output configuration is pull-down, not the standard
By these means these ports may be configured to operate as
connection to a wired-or, single-wire bus (e.g. DIGITbus or
I
S0 to 7
r/w1:
r/w0:
A0 to 7
r/w1:
r/w0:
2
r/w
r/w
r/w
r/w
r/w
r/w
C) with external pull-up resistor.
UxNS
UxDPM
UxSLOW
UxLVL
Mode enabled for these ports, and SR0.PSLW set to 1)
push-pull.
SG7_2
SG7_3
D7
7
A7
S7
S7
0
0
0
0
7
7
7
SG6_2
SG6_3
D6
A6
S6
S6
6
0
0
0
0
6
6
6
Normal/Special Mode Flag 0 to 7
Special Mode. Special hardware drives pin.
Normal Mode. Data latch drives pin.
Double Pull-Down Mode
Output driver is pull-down,
I
Standard.
Slow Flag 0 to 7
Output driver is in Port Slow mode
Output driver is in Port Fast mode
Automotive Flag 0 to 7
Schmitt trigger input level is Automotive
Schmitt trigger input level is CMOS
shs
SG5_2
SG5_3
(Port Slow mode) doubled.
Universal Port x Input Level Register
D5
A5
Universal Port x Normal-Special /
Segment 2 Register
S5
Universal Port x Double Pull-Down
Mode / Segment 3 Register
Universal Port x Slow Mode Register
S5
5
0
0
0
0
5
5
5
SG4_2
SG4_3
D4
A4
S4
S4
4
0
0
0
0
4
4
4
shs
is doubled (with Port Slow
SG3_2
SG3_3
CDC 32xxG-C
S3
D3
S3
A3
3
0
0
0
0
3
3
3
SG2_2
SG2_3
S2
D2
S2
A2
2
0
0
0
0
2
2
2
SG1_2
SG1_3
S1
D1
S1
A1
0
0
0
1
0
1
1
1
SG0_2
SG0_3
S0
D0
S0
A0
0
0
0
0
0
0
0
0
103
Port
LCD
Res
Port
LCD
Res
Res
Res