CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 141

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
22. DMA Controller
The DMA controller allows transferring data fields between
internal memory and either an external IC via U-Ports (G-
Bus), or an SPI module, with minimum CPU interaction.
DMA transfers can be triggered by the interrupt source out-
put of the corresponding module (self timed), a dedicated
DMA Timer output or a port interrupt.
The G-Bus is intended to support the operation of external
LCD driver ICs (e.g. SED1560 by Epson):
The DMA module copies 8bit pixel data bytes by direct mem-
ory access (DMA) to the external IC’s graphic RAM with help
of that IC’s internal autoincrement address counter, and with-
out CPU interaction. Other off-chip registers, allowing control
of the display behavior (blinking, scrolling, etc.), have to be
addressed by CPU operations.
In SPI mode, the DMA module copies data bytes by direct
memory access (DMA) to the SPIxD data register, self timed
or under timing of the DMA timer and without CPU interac-
22.1. Functions
Fig. 22–1:
The DMA Controller transfers bytes (8 bit) between I/O mod-
ules and memory. One transfer is called a DMA cycle. The
transfer of a block of bytes is called a DMA sequence.
Micronas
Controller
SRAM
ROM
Flash
CPU
Bus
System Block Diagram
3
I/O-Module
Controller
3
DMA
ICU
4
June 12, 2003; 6251-579-1PD
tion, to construct long serial data transfer sequences. It frees
the CPU of repeatedly reloading data, e.g. under interrupt
control.
Features
– 3 DMA channels:
– 256 byte maximum DMA block size
– one byte DMA block alignment
– CPU cycle steal
– Interrupt on DMA sequence finished
The DMA Controller contains one DMA channel logic for
each DMA channel, the priority encoder, the control logic, the
DMA vector base register, address and cycle count buffer,
and the bus interface (see Fig. 22–2 on page 140).
The DMA vector base register points to the beginning of the
DMA table which is filled with a DMA vector for each DMA
channel. Location zero contains the default vector and is not
assigned to any DMA channel. Each DMA vector is com-
posed of a 24 bit source/destination address and a 8 bit
cycle counter value (see Fig. 22–5 on page 141).
A DMA cycle is divided in a sequence of three steps:
1. Output Address of the DMA vector and read source/desti-
nation address and cycle counter.
2. Output Address of the DMA vector and write back incre-
mented source/destination address and decremented cycle
counter.
3. Output source/destination address and write/read data to/
from I/O module.
Each step is one bus access which holds the CPU (cycle
stealing). The DMA Controller generates the necessary con-
trol signals for above bus accesses.
An I/O module requests a DMA cycle via its interrupt source
output which is connected to the DMA request input (DREQ)
of the corresponding DMA channel logic. The DMA interrupt
output (DINT) is connected to the ICU instead where it indi-
cates the end of a DMA sequence (see Fig. 22–3 on
page 141). The signal DINT is connected to the G-Bus logic
too, where it sets a flag indicating the end of the DMA
sequence (see Fig. 22–4 on page 141).
direct 8bit data read or write between memory and U-
Ports U5 and U7 (G-Bus),
direct 8bit data read or write between memory and SPI0,
direct 8bit data read or write between memory and SPI1
CDC 32xxG-C
139