CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 72

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
A read access to byte 0 of the SSC latches the bytes 1 and
2. This mechanism grants consistent read access to the
SSC.
Reading SEC latches MIN and HR. Writing HR simulta-
neously loads MIN and SEC to the corresponding counters.
This mechanism allows consistent read and write access.
Since reading and writing use the same latches, don’t mix
these access types. Wait one f
read accesses to RTC because it lasts one bus cycle until a
written value gets valid.
HR
r/w0 to 23:
MIN
r/w0 to 59:
SEC
r/w0 to 59:
SEL
RTC
r1:
r0:
70
r/w
r/w
r/w
r/w
r/w
r/w
r/w
SSC
RTC
RTCC
WUS
r
r
r
r
RTC
WP7
x
x
x
x
x
x
x
7
7
7
7
WP6
x
x
x
x
x
x
x
x
6
6
6
6
Minute Counter
Hour Counter
Second Counter
Select RTC Output (Table 7–2)
Real Time Clock
RTC was trigger source
No trigger
WP5
Sub Second Counter
Real Time Counter
RTC Control Register
Wake-Up Source Register
x
x
x
x
x
x
5
5
5
5
WP4
No HW reset
No HW reset
No HW reset
No HW reset
x
x
Bit 15 to 8
x
x
4
Bit 7 to 0
4
4
4
WP3
IO
x
x
x
3
3
3
3
SEC
MIN
cycle between write and
WP2
SEL
HR
Bit 19 to 16
x
x
x
2
2
2
2
WP9
WP1
x
x
1
1
1
1
WP8
WP0
June 12, 2003; 6251-579-1PD
x
x
0
0
0
0
3
2
1
0
Res
3
2
1
0
Res
0
Res
1
0
Res
Offs
Offs
Offs
Offs
w1:
w0:
WPx
r1:
r0:
w1:
w0:
For proper interrupt generation some peculiarities in operat-
ing this register have to be considered. All set bits must be
cleared by writing back the whole pattern that was read
before. Always read and clear (write back) the whole register
(byte 0 first) even if only flags in byte 0 are in use. Every
write access to byte 1 will produce an interrupt as long as
WUS contains a one.
MODy
Trigger mode for Wake Port WPx+y. For assignment of Wake
Port and mode field please refer table 7–7.
CLK
PER
ENA
r/w1:
r/w0:
OE
r/w1:
r/w0:
DEL
r/w1 to 31:
r/w0:
A write access to DEL immediately loads the 5-bit down
counter. The delay time defines the duration of the Wake Out
signal (Fig. 7–5).
AST
r/w1:
r/w0:
RTC
r/w1:
r/w
r/w
r/w
r/w
WPMx
POL
WSC
ENA
x
x
x
7
7
7
OE
x
6
6
6
Clear
No modification
Wake Port x
Wake Port was trigger source
No trigger
Clear
No modification
Trigger Mode (Table 7–3)
Select Polling Clock (Table 7–5)
Select Polling Period (Table 7–4)
Enable Polling Module
enable
disable
Enable Polling Output
enable
disable
Select Polling Delay Time
Delay time = DEL/f
Delay time = 32/f
Alternative Strobe
Alternative strobe input
Wake out signal from Polling Logic
RTC Wake-up Enable
enable
CLK
MOD1
Wake Port x Mode Register
Polling Register
Wake Source Control
x
x
5
5
5
0x00 after UVDD power-up
No HW reset
x
x
4
4
4
PRELIMINARY DATA SHEET
0x00
PC
x
x
3
3
PC
3
DEL
AST
2
2
2
PER
MOD0
RTC
1
1
1
Micronas
P
0
0
0
0
Res
1
0
Res
0
Res
Offs
Offs
Offs