CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 140

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
21.2. Registers
Please refer to section “Universal Port Registers” for details
on segment register layout.
LCDSLV
Select the mode of the LCD module.
w1:
w0:
21.3. Application Hints for Cascading LCD Modules
21.3.1. Power On and Start Up Procedure
1. The SW in master and slave configures the corresponding
IC.
Table 21–1:
2. Optionally the slave signals to the master via handshake
link or an inter processor interface (IPI) that it is ready to dis-
play.
3. The slave continuously scans the inputs LCD-CLK-IN and
LCD-SYNC-IN for the bit combination “01” (SW debouncing
required).
4. The master LCD module is switched on. LCD-CLK-OUT
and LCD-SYNC-OUT switch to “01”.
5. The slave CPU detects the bit combination “01” and imme-
diately switches on the slave LCD module. The slave LCD
now generates a display.
Note: During the time that the slave needs to detect the bit
combination “01”, master and slave operate asynchronously.
Suggestion: limit time to approximately 100 to 200ms.
6. The LCD modules now operate in controlled synchroniza-
tion.
21.3.2. Operation
In order to obtain optimum synchronization of LCD switch-
over, a change of display must be coordinated between mas-
ter and slave (preferably via IPI) in such a way, that the time
138
Master
Load LCD display register.
Clear flag LCDSLV.
LCD-CLK-OUT, and
LCD-SYNC-OUT:
Configure universal ports
as Special Out Ports.
w LCDSLV
ULCDLD
0
7
LCD Module is Slave
LCD module is slave.
LCD module is master.
x
0
6
Suggested sequence
Universal Port LCD Load Register
x
0
5
x
0
4
Slave
Load LCD display register.
Set flag LCDSLV.
LCD-CLK-IN, and
LCD-SYNC-IN:
Configure universal ports
as Special In Ports.
x
0
3
x
0
2
x
0
1
June 12, 2003; 6251-579-1PD
x
0
0
Res
A write access to this memory location simultaneously loads
all segment information of all U-Ports in LCD mode to the
display.
21.2.1. Special Register Layout of U-Port 4
U4.0 to U4.3 provide backplane signals in LCD Mode. To
operate any ports as LCD segment driver it is necessary to
switch all these ports to LCD mode. This has to be done by
setting flags U4MODE.L0 through U4MODE.L3.
As backplane ports U4.0 to U4.3 require no segment data
setting, SG0_0 through SG3_3 bits are not available in U4
registers.
lag between write accesses to ULCDLD of the master and of
the slave is kept as small as possible. Suggestion: Lower ms
range or customer specification.
21.3.3. Power Off Procedure
1. (Optional) The processor which decides that the display is
to be switched off signals this to the other via IPI.
2. The slave continuously scans the inputs LCD-CLK-IN and
LCD-SYNC-IN for the bit combination “11” (SW debouncing
required).
3. The master LCD module is switched off. LCD-CLK-OUT
and LCD-SYNC-OUT switch to “11”.
4. The slave CPU detects the bit combination “11” and imme-
diately switches off the slave LCD module.
Note: Keep time delay as short as when switching on.
5. All LCD ports output a low signal now. The LCD display is
now inactive.
PRELIMINARY DATA SHEET
Micronas