SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 971
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
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6438G–ATARM–19-Apr-11
Note:
Note:
3. Write the starting source address in the DMAC_SADDRx register for channel x.
4. Write the channel configuration information into the DMAC_CFGx register for channel
5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
7. Make sure that the LLI.DMAC_DADDRx register location of all LLIs in memory point to
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register
9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
11. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 6 as shown in
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
16. Source and destination request single and chunk DMAC transactions to transfer the
17. The DMAC_CTRLAx register is written out to system memory. The DMAC_CTRLAx
x.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
the last) are set as shown in Row 6 of
LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in
Row 1 of
list items.
the last) are non-zero and point to the next Linked List Item.
the start destination buffer address proceeding that LLI fetch.
locations of all LLIs in memory is cleared.
DMAC_SPIPx register for channel x.
the DMAC_DPIPx register for channel x.
ing to the DMAC_EBCISR register.
Table 41-2 on page
Linked List item.
is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN
register is enabled.
buffer of data (assuming non-memory peripherals). DMAC acknowledges at the com-
pletion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
register is written out to the same location on the same layer
(DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the
DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer
The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs)
setup up in memory, although fetched during a LLI fetch, are not used.
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register although fetched is
not used.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface
source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DST_PER bits, respectively.
Table
41-2.
960.
Figure 41-5 on page 959
Table 41-2 on page 960
shows a Linked List example with two
while the
SAM9G45
971
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