SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1175
SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 1175 of 1196
- Download datasheet (20Mb)
49.2.4
49.2.4.1
49.2.5
49.2.5.1
49.2.5.2
6438G–ATARM–19-Apr-11
Static Memory Controller (SMC)
Serial Synchronous Controller (SSC)
SMC: SMC Delay Access
SSC: Data sent without any frame synchro
SSC: Unexpected delay on TD output
In this document, the Access is “Read-write” in the Register Mapping Table (SMC_DELAY1 to
SMC_DELAY8 rows), and in the SMC DELAY I/O Register.
The current access is “Write-only”.
None
When SSC is configured with the following conditions:
The data is sent but there is not any toggle of the TF line
Transmit STTDLY must be different from 0.
When SSC is configured with the following conditions:
Unexpected delay of 2 or 3 system clock cycles is added to TD output.
None
• RF is in input,
• TD is synchronized on a receive START (any condition: START field = 2 to 7)
• TF toggles at each start of data transfer
• Transmit STTDLY = 0
• Check TD and TF after a receive START,
• TCMR.STTDLY more than 0
• RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge
• RFMR.FSOS = None (input)
• TCMR.START = Receive Start
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
SAM9G45
1175
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