SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 537
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 537 of 1196
- Download datasheet (20Mb)
32.7.4
Name:
Addresses:
Access:
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = counter is incremented on rising edge of the clock.
1 = counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = counter clock is not stopped when RB loading occurs.
1 = counter clock is stopped when RB loading occurs.
6438G–ATARM–19-Apr-11
LDBDIS
WAVE
31
23
15
–
–
7
0
0
1
1
0
0
0
0
1
1
1
1
TC Channel Mode Register: Capture Mode
BURST
LDBSTOP
CPCTRG
30
22
14
TC_CMRx [x=0..2] (WAVE = 0)
0xFFF7C004 (0)[0], 0xFFF7C044 (0)[1], 0xFFF7C084 (0)[2], 0xFFFD4004 (1)[0],
0xFFFD4044 (1)[1], 0xFFFD4084 (1)[2]
Read-write
–
–
6
TCCLKS
0
1
0
1
0
0
1
1
0
0
1
1
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
29
21
13
–
–
–
5
BURST
0
1
0
1
0
1
0
1
28
20
12
–
–
–
4
Clock Selected
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
CLKI
27
19
11
–
–
3
LDRB
ABETRG
26
18
10
–
2
TCCLKS
25
17
–
9
1
ETRGEDG
SAM9G45
LDRA
24
16
–
8
0
537
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