SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 185

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

21.6
Figure 21-2.
21.7
21.7.1
21.7.2
6438G–ATARM–19-Apr-11
External Memory Mapping
Connection to External Devices
Data Bus Width
Byte Write or Byte Select Access
SMC
Memory Connections for Eight External Devices
NCS[0] - NCS[7]
D[31:0]
A[25:0]
NWE
NRD
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address
up to 64 Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see
A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for
32-bit memory.
A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is con-
trolled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select.
Figure 21-3
connect a 512K x 16-bit memory on NCS2.
as a single 32-bit memory
Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of
write access: byte write or byte select access. This is controlled by the BAT field of the
SMC_MODE register for the corresponding chip select.
shows how to connect a 512K x 8-bit memory on NCS2.
8 or 16 or 32
NCS0
NCS1
Figure 21-5
NCS2
A[25:0]
Memory Enable
Output Enable
Write Enable
D[31:0] or D[15:0] or
D[7:0]
NCS3
Memory Enable
Figure
NCS4
Memory Enable
NCS5
shows two 16-bit memories connected
NCS6
Memory Enable
21-2).
NCS7
Memory Enable
Memory Enable
Memory Enable
Figure 21-4
Memory Enable
SAM9G45
shows how to
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