SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 247

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 22-21. Automatic Update During AUTO-REFRESH Command and SDRAM Access
22.4.4.2
6438G–ATARM–19-Apr-11
COMMAND
SDCLK
BA[1:0]
A[12:0]
CKE
Power-down Mode
NOP
PRCHALL
0
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode,
power consumption is greater than in self refresh mode. This state is similar to normal mode (No
low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers
are deactivated as soon the SDRAM device is no longer accessible. In contrast to self refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the
refresh operation. In order to exit low-power mode, a NOP command is required in the case of
Low-power SDR-SDRAM and SDR-SDRAM devices. In the case of Low-power DDR-SDRAM
devices, the controller generates a NOP command during a delay of at least TXP. In addition,
Low-power DDR-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum
period of TCKE periods.
The exit procedure is faster than in self refresh mode. See
DDRSDRC returns to power-down mode as soon as the SDRAM device is not selected. It is
possible to define when power-down mode is enabled by setting the register LPR, timeout com-
mand bit.
• 00 = Power-down mode is enabled as soon as the SDRAM device is not selected
• 01 = Power-down mode is enabled 64 clock cycles after completion of the last access
• 10 = Power-down mode is enabled 128 clock cycles after completion of the last access
Trp
NOP
ARFSH
2
Trfc
NOP
Pasr-Tcr-Ds
MRS
Update Extended mode
register
Tmrd
NOP
Figure 22-22 on page
ACT
0
SAM9G45
248. The
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