SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1102
SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
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45.11 Register Configuration Guide
45.11.1
45.11.2
1102
SAM9G45
STN Mode Example
TFT Mode Example
Program the PIO Controller to enable LCD signals.
Enable the LCD controller clock in the Power Management Controller.
STN color(R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 Mhz
Data rate: 320*240*70*3/8 = 2.016 MHz
HOZVAL= ((3*320)/8) - 1
LINEVAL= 240 -1
CLKVAL = (60 MHz/2.016 MHz) - 1 = 29
LCDCON1= CLKVAL << 12
LCDCON2 = LITTLEENDIAN | SINGLESCAN | STNCOLOR | DISP8BIT| PS8BPP;
LCDTIM1 = 0;
LCDTIM2 = 10 | (10 << 21);
LCDFRMCFG = (HOZVAL << 21) | LINEVAL;
LCDMVAL = 0x80000004;
DMAFRMCFG = (7 << 24) + (320 * 240 * 8) / 32;
This example is based on the NEC TFT color LCD module NL6448BC20-08
TFT 640*480, 16-bit single scan, 60 frames/sec, pixel clock frequency = [21MHz..29MHz] with a
typical value = 25.175 MHz.
The Master clock must be (n + 1)*pixel clock frequency
HOZVAL = 640 - 1
LINEVAL = 480 - 1
If Master clock is 100 MHz
CLKVAL = (100 MHz/ 25.175 MHz) - 1= 3
VFP = (12 -1), VBP = (31-1), VPW = (2-1), VHDLY= (2-1)
HFP = (16-1), HBP = (48 -1), HPW= (96-1)
LCDCON1= CLKVAL << 12
LCDCON2 = LITTLEENDIAN | CLKMOD | INVERT_CLK | INVERT_LINE | INVERT_FRM |
PS16BPP | SINGLESCAN | TFT
LCDTIM1 = VFP | (VBP << 8) | (VPW << 16) | (VHDLY << 24)
LCDTIM2 = HBP | (HPW << 8) | (HFP << 21)
LCDFRMCFG = (HOZVAL << 21) | LINEVAL
LCDMVAL = 0
DMAFRMCFG = (7 << 24) + (640 * 480* 16) / 32;
.
6438G–ATARM–19-Apr-11
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