SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 35
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 35 of 1196
- Download datasheet (20Mb)
9.4.6
9.4.7
6438G–ATARM–19-Apr-11
ARM9EJ-S Operating Modes
ARM9EJ-S Registers
Minimum interrupt latency is maintained across both ARM state and Java state. Since byte
codes execution can be restarted, an interrupt automatically triggers the core to switch from
Java state to ARM state for the execution of the interrupt handler. This means that no special
provision has to be made for handling interrupts while executing byte codes, whether in hard-
ware or in software.
In all states, there are seven operation modes:
Mode changes may be made under software control, or may be brought about by external inter-
rupts or exception processing. Most application programs execute in User Mode. The non-user
modes, known as privileged modes, are entered in order to service interrupts or exceptions or to
access protected resources.
The ARM9EJ-S core has a total of 37 registers.
Table 9-1
Table 9-1.
System Mode
• User mode is the usual ARM program execution state. It is used for executing most
• Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data
• Interrupt (IRQ) mode is used for general-purpose interrupt handling
• Supervisor mode is a protected mode for the operating system
• Abort mode is entered after a data or instruction prefetch abort
• System mode is a privileged user mode for the operating system
• Undefined mode is entered when an undefined instruction exception occurs
• 31 general-purpose 32-bit registers
• 6 32-bit status registers
application programs
transfer or channel process
User and
R10
R11
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
shows all the registers in all modes.
ARM9TDMI Modes and Registers Layout
Supervisor
Mode
R10
R11
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Abort Mode
R10
R11
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Undefined
Mode
R10
R11
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Interrupt
Mode
R10
R11
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
SAM9G45
Fast Interrupt
R10_FIQ
R11_FIQ
R8_FIQ
R9_FIQ
Mode
R0
R1
R2
R3
R4
R5
R6
R7
35
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