SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1090
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 1090 of 1196
- Download datasheet (20Mb)
Figure 45-6. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1
Figure 45-7. TFT Panel Timing (Line Expanded View), CLKMOD = 1
1090
LCDHSYNC
LCDVSYNC
LCDHSYNC
LCDVSYNC
LCDDOTCK
LCDHSYNC
LCDDOTCK
LCDVSYNC
LCDDEN
LCDDOTCK
LCDDEN
LCDDEN
SAM9G45
LCDD
LCDD
LCDD
VHDLY+1
VHDLY+1
Vertical Back Porch = VBP Lines
VHDLY+1
--------------------------- -
f
LCDVSYNC
Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation:
where:
In STN Mode:
1
• HOZVAL determines de number of LCDDOTCK cycles per line
• LINEVAL determines the number of LCDHSYNC cycles per frame, according to the
HPW+1
HPW+1
expressions shown below:
(VPW+1) Lines
=
VHDLY
------------------------------------------------------------------------------------------------------------------------- - VBP
HBP+1
HBP+1
HOZVAL
+
1 PCLK
1 PCLK
HPW
=
Horizontal_display_size
-------------------------------------------------------------- - 1
Line Period
+
Line Period
HBP
f
Number_data_lines
LCDDOTCK
Frame Period
1/2 PCLK 1/2 PCLK
+
1/2 PCLK 1/2 PCLK
HOZVAL
+
HOZVAL+1
HOZVAL+1
HFP
–
+
4
+
LINEVAL
Vertical Fron t Porch = VFP Lines
+
6438G–ATARM–19-Apr-11
VFP
HFP+VHDLY+2
HFP+VHDLY+2
+
1
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