SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 642

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

34.5
Table 34-1.
34.6
34.6.1
34.6.2
34.6.3
642
Pin Name
RF
RK
RD
TF
TK
TD
Pin Name List
Product Dependencies
SAM9G45
I/O Lines
Power Management
Interrupt
I/O Lines Description
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
Table 34-2.
The SSC is not continuously clocked. The SSC interface may be clocked through the Power
Management Controller (PMC), therefore the programmer must first configure the PMC to
enable the SSC clock.
The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling interrupts requires programming the AICbefore configuring the SSC.
Instance
Pin Description
Receiver Frame Synchro
Receiver Clock
Receiver Data
Transmitter Frame Synchro
Transmitter Clock
Transmitter Data
SSC0
SSC0
SSC0
SSC0
SSC0
SSC0
SSC1
SSC1
SSC1
SSC1
SSC1
SSC1
I/O Lines
Signal
RD0
RK0
RD1
RF1
RK1
TD1
RF0
TD0
TK0
TF1
TK1
TF0
I/O Line
PD11
PD15
PD13
PD10
PD14
PD12
PD3
PD5
PD4
PD2
PD1
PD0
Input/Output
Input/Output
Input/Output
Input/Output
6438G–ATARM–19-Apr-11
Output
Type
Input
Peripheral
A
A
A
A
A
A
A
A
A
A
A
A