SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1183

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6438G–ATARM–19-Apr-11
Doc. Rev
6438D
Doc. Rev
6438C
Comments (Continued)
LCD Controller (LCDC):
Section 45.12.12 “LCD Timing Configuration Register
written to 1’ added to VHDLY definition.
Parallel Input/Output Controller (PIO):
- DELAY Registers were addded in a
description added in a
-
Register”and
In
Clear Output Data”
All ‘slewrate’ changed into ‘drive’.
All ‘IO’ changed into ‘I/O’.
All
Any extra ‘Controller’ or ‘Controller PIO’ removed.
Static Memory Controller (SMC):
Table 21-5 removed from
21-8
USB Host Port:
Section 37. “USB High Speed Host Port (UHPHS)”
Comments
Introduction:
Section 3. “Signal Description”
concerning NRST configuration.
Section 4. “Package and
Boot Program:
Section 11.5.2.1 “Supported External Crystal/External
RSTC:
Section 12.5 “Reset Controller (RSTC) User Interface” Table 12-1
0x0000 0001.
“Write Protected Registers”
Section 30.6.11 “PIO Clear Output Data
Section 30.6 “Parallel Input/Output Controller (PIO) User Interface”
instead.
Section 30.6.32 “PIO Write Protect Status
Section 30.6.30 “PIO I/O Delay
Pinout”,
Section 21.8.6 “Reset Values of Timing
description added, together with
,
Table
Table 4-1
Section 30.4.12 “Programmable I/O Delays”
3-1, in
Register”, “P0-P31: Set Output Data” changed into “P0-P31:
updated.
“Reset/Test”
, HS (High Speed) was added to the title.
1”, ‘-’ replaced by ‘1’ for bit 31, and ‘Bit 31 must be
Clocks”, ...”supports 12 MHz”...
Register”.
Register”.
description, NRST pin updated with note
Section 30.6.31 “PIO Write Protect Mode
Parameters”. Cross-referenced
Mode register backup reset value is
headers now start with ‘PIO’ only.
and associated register
Table
SAM9G45
Change
Request
Ref.
6685
6715
6742
6644
Change
Request
Ref.
6600
6639
6598
6639
1183