SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 263

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.7.5
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• TRFC: Row Cycle Delay
Reset Value is 8 cycles.
This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Num-
ber of cycles is between 0 and 31
• TXSNR: Exit Self Refresh Delay to Non-read Command
Reset Value is 8 cycles.
This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is
between 0 and 255. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices
and Low-power DDR-SDRAM, this field is equivalent to TXSR timing.
• TXSRD: ExiT Self Refresh Delay to Read Command
Reset Value is C8.
This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 255 cycles.This field is unique to DDR-SDRAM devices.
• TXP: Exit Power-down Delay to First Command
Reset Value is 3.
This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between
0 and 15 cycles. This field is unique to Low-power DDR-SDRAM devices and DDR2-SDRAM devices.
6438G–ATARM–19-Apr-11
31
23
15
–
7
–
DDRSDRC Timing 1 Parameter Register
30
22
14
DDRSDRC_T1PR
Read-write
See
–
6
–
Table 22-9
29
21
13
–
5
–
28
20
12
–
4
TXSRD
TXSNR
“DDRSDRC Write Protect Mode Register” on page
27
19
11
3
TRFC
26
18
10
2
TXP
25
17
9
1
SAM9G45
271.
24
16
8
0
263